Process execution semantics in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Process sensitivity list behavior

Consider the following VHDL process. What is the output on signal out_sig after the process executes once, assuming clk = '1' and rst = '0' at the start?

process(clk, rst)
begin
  if rst = '1' then
    out_sig <= '0';
  elsif rising_edge(clk) then
    out_sig <= not out_sig;
  end if;
end process;

VHDL

signal out_sig : std_logic := '0';
signal clk, rst : std_logic;
-- Initial values: clk = '1', rst = '0'
-- Process runs once

A out_sig = 'X' (undefined)

B out_sig = '0'

C out_sig = '1'

D No change to out_sig

💡 Hint

Remember that the process triggers on changes to clk or rst, and the rising_edge function checks for a 0 to 1 transition. At simulation start with clk='1', there is no rising edge event.

At simulation time 0, the process executes once. rst='0', so reset skipped. rising_edge(clk) requires clk='1', clk'EVENT=true, and clk'LAST_VALUE='0', but at t=0 with clk='1', no event occurred, so false. No assignment, out_sig remains '0'.

🧠 Conceptual

intermediate

Process execution and delta cycles

In VHDL simulation, what happens when multiple processes are sensitive to the same signal and that signal changes?

Choose the correct statement about process execution and delta cycles.

A Processes execute sequentially in an arbitrary order within the same delta cycle, and signal updates take effect in the next delta cycle.

B All sensitive processes execute simultaneously in the same delta cycle.

C Only one process executes per delta cycle, others wait for the next clock cycle.

D Processes execute only after all signals stabilize, ignoring delta cycles.

💡 Hint

Think about how VHDL schedules processes and updates signals in simulation time.

When a signal changes, all processes sensitive to it are scheduled to run in the same delta cycle but execute sequentially in an arbitrary order. Signal assignments take effect after the delta cycle, so other processes see old values during the current delta cycle.

🔧 Debug

advanced

Unexpected output due to missing sensitivity list

Given this VHDL process, what is the main reason out_sig does not update as expected?

process
begin
  wait until clk = '1';
  out_sig <= not out_sig;
end process;

A The signal assignment uses blocking instead of non-blocking assignment.

B Process lacks a sensitivity list, so it never triggers automatically.

C The wait statement causes a simulation deadlock.

D The process runs only once and never repeats.

💡 Hint

Consider how processes with wait statements behave in VHDL simulation, especially level-sensitive conditions.

This process uses level-sensitive 'wait until clk = "1"'. On rising edge, it toggles and loops back. If clk remains '1', the wait condition is true, process does not suspend, loops infinitely toggling in zero time, causing simulation deadlock (infinite delta cycles). Use 'wait until rising_edge(clk)' for proper edge sensitivity.

📝 Syntax

advanced

Identify the syntax error in process declaration

Which option contains the correct syntax for a VHDL process with sensitivity list for signals a and b?

A

process(a, b)
begin
  -- process body
end process;

B

process a, b is
begin
  -- process body
end process;

C

process(a b)
begin
  -- process body
end process;

D

process(a; b)
begin
  -- process body
end process;

💡 Hint

Check the punctuation and keywords used in the process header.

The correct syntax uses parentheses with signals separated by commas. Option A correctly uses process(a, b). Options B, C, and D have syntax errors: missing parentheses, missing commas, or wrong separators.

🚀 Application

expert

Process execution order with multiple signals

Given two processes below, what is the value of out1 and out2 after signal sig changes from '0' to '1' in simulation?

signal sig : std_logic := '0';
signal out1, out2 : std_logic := '0';

process(sig)
begin
  out1 <= sig;
end process;

process(sig)
begin
  out2 <= not sig;
end process;

A out1 = '1', out2 = '1'

B out1 = '0', out2 = '0'

C out1 = '0', out2 = '1'

D out1 = '1', out2 = '0'

💡 Hint

Remember that signal assignments take effect after the process completes and delta cycles separate updates.

sig changes to '1', generating an event. Both processes sensitive to sig are resumed in the current delta cycle, execute sequentially in arbitrary order, and read the new value sig='1'. out1 <= '1'; out2 <= not '1' = '0'. The <= assignments schedule updates for the next delta cycle. Thus, after the delta cycle, out1='1', out2='0'.

Practice

1. What happens when a signal in a VHDL process's sensitivity list changes?

easy

A. The entire process executes from the beginning once.

B. Only the changed signal is updated inside the process.

C. The process pauses until the signal stabilizes.

D. The process executes partially based on the changed signal.

Solution

1. Step 1: Understand sensitivity list trigger

   In VHDL, a process runs fully whenever any signal in its sensitivity list changes.

2. Step 2: Execution behavior

   The process does not partially run or pause; it executes all statements sequentially from the start.

3. Final Answer:

   The entire process executes from the beginning once. -> Option A

4. Quick Check:

   Process runs fully on sensitivity change = A [OK]

Hint: Process runs fully on any sensitivity list signal change [OK]

Common Mistakes:

• Thinking only changed signals update inside process
• Believing process pauses or partially runs
• Confusing process with concurrent statements

2. Which of the following is the correct syntax to declare a process with signals clk and reset in its sensitivity list?

easy

A. process(clk reset) begin ... end process;

B. process begin clk, reset; ... end process;

C. process(clk; reset) begin ... end process;

D. process(clk, reset) begin ... end process;

Solution

1. Step 1: Check sensitivity list syntax

   The sensitivity list must be inside parentheses, with signals separated by commas.

2. Step 2: Validate options

   process(clk, reset) begin ... end process; uses correct syntax: process(clk, reset) begin ... end process; Options A, B, and D have syntax errors (missing commas, wrong separators).

3. Final Answer:

   process(clk, reset) begin ... end process; -> Option D

4. Quick Check:

   Correct sensitivity list syntax uses commas = C [OK]

Hint: Use commas between signals in sensitivity list parentheses [OK]

Common Mistakes:

• Omitting commas between signals
• Using semicolons instead of commas
• Placing signals outside parentheses

3. Given the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

What happens to count when clk changes from '0' to '1'?

medium

A. Process causes a syntax error.

B. count resets to 0.

C. count increments by 1.

D. count remains unchanged.

Solution

1. Step 1: Identify trigger condition

   The process triggers on any change of clk. The if rising_edge(clk) checks for a 0 to 1 transition.

2. Step 2: Effect on count

   When clk rises, count increments by 1 as per the assignment.

3. Final Answer:

   count increments by 1. -> Option C

4. Quick Check:

   Rising edge triggers increment = D [OK]

Hint: Rising edge on clk triggers count increment [OK]

Common Mistakes:

• Confusing rising_edge with falling_edge
• Assuming count resets instead of increments
• Thinking process syntax is incorrect

4. Consider this VHDL process:

process(clk)
begin
  if clk = '1' then
    signal_a <= '0';
  else
    signal_a <= '1';
  end if;
end process;

What is the main problem with this process?

medium

A. It will cause a syntax error due to missing sensitivity signals.

B. It may create a latch because it lacks a clock edge condition.

C. It will never execute because clk is not in sensitivity list.

D. It updates signal_a asynchronously, which is always correct.

Solution

1. Step 1: Analyze sensitivity list and conditions

   The process triggers on any clk change, but uses level check (clk = '1') instead of edge detection.

2. Step 2: Understand latch creation

   Because assignments depend on clk level without edge detection, synthesis tools may infer a latch to hold signal_a's value.

3. Final Answer:

   It may create a latch because it lacks a clock edge condition. -> Option B

4. Quick Check:

   Level check without edge causes latch = B [OK]

Hint: Use rising_edge or falling_edge to avoid latches [OK]

Common Mistakes:

• Assuming missing sensitivity signals cause syntax error
• Thinking process won't execute without edge
• Believing asynchronous updates are always safe

5. You want to design a VHDL process that increments a counter only on the rising edge of clk and asynchronously resets it to zero when reset is '1'. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

B. process(clk)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

D. process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   Asynchronous reset requires reset in sensitivity list and checked before clock edge.

2. Step 2: Check process structure

   process(clk, reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   checks reset = '1' first, then rising_edge(clk), correctly implementing async reset and sync count increment.

3. Step 3: Validate other options

   process(clk)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   misses reset in sensitivity list (wrong for async reset).

   process(reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   triggers only on reset, ignoring clk.

   process(clk, reset)
   begin
     if rising_edge(clk) then
       if reset = '1' then
         count <= 0;
       else
         count <= count + 1;
       end if;
     end if;
   end process;

   treats reset synchronously inside clock edge.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then count <= 0; elsif rising_edge(clk) then count <= count + 1; end if; end process; -> Option A

5. Quick Check:

   Async reset checked first with reset in sensitivity list = A [OK]

Hint: Put async reset first and include it in sensitivity list [OK]

Common Mistakes:

• Omitting reset from sensitivity list for async reset
• Checking reset inside clock edge (sync reset)
• Using wrong sensitivity list signals