Combinational process vs sequential process in VHDL - Visual Side-by-Side Comparison

Concept Flow - Combinational process vs sequential process

Start

↓

Process type?

↓

Combinational

↓

No clock

↓

Output depends

↓

only on inputs

↓

Immediate

↓

End

The flow shows choosing between combinational and sequential processes, highlighting their triggers and output behavior.

Execution Sample

VHDL

process(a, b)
begin
  y <= a and b;
end process;

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

Two VHDL processes: one combinational (output y updates immediately when a or b change), one sequential (q updates on clock rising edge).

Execution Table

Step	Process Type	Trigger/Event	Condition	Action	Output Change
1	Combinational	a or b changes	N/A	Evaluate y <= a and b	y updates immediately
2	Combinational	a or b changes	N/A	Evaluate y <= a and b	y updates immediately
3	Sequential	clk rising edge	rising_edge(clk) = True	q <= d	q updates on clock
4	Sequential	clk stable or falling	rising_edge(clk) = False	No action	q unchanged
5	Combinational	a or b changes	N/A	Evaluate y <= a and b	y updates immediately
6	Sequential	clk rising edge	rising_edge(clk) = True	q <= d	q updates on clock

💡 Process waits for next input change (combinational) or clock rising edge (sequential) to continue.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6
a	0	1	1	1	1	0	0
b	0	1	0	0	0	1	1
y	0	1	1	1	1	0	0
clk	0	0	1	1	0	0	1
d	0	0	0	1	1	1	1
q	0	0	0	1	1	1	1

Key Moments - 3 Insights

Why does the combinational process update output immediately when inputs change?

Because the combinational process sensitivity list includes inputs (a, b), so any change triggers immediate evaluation (see execution_table steps 1, 2, 5).

Why does the sequential process update output only on clock rising edge?

Because it uses 'if rising_edge(clk)' condition, so output q changes only when clock signal rises (see execution_table steps 3 and 6).

What happens if inputs change but clock does not rise in sequential process?

No output change occurs in sequential process since it waits for clock event (see execution_table step 4).

Visual Quiz - 3 Questions

Look at the execution_table, at which step does the sequential process update q?

A Step 3

B Step 4

C Step 2

D Step 5

💡 Hint

Check the 'Process Type' and 'Action' columns for when q is assigned.

According to variable_tracker, what is the value of y after Step 2?

A 0

B 1

C Undefined

D Same as before

💡 Hint

Look at the 'y' row under 'After Step 2' column.

If the clock signal never rises, what happens to q in the sequential process?

A q toggles randomly

B q updates immediately

C q never changes

D q updates when inputs change

💡 Hint

Refer to execution_table step 4 where no clock rising edge means no q update.

Concept Snapshot

Combinational process: triggers on input changes, outputs update immediately.
Sequential process: triggers on clock edges, outputs update only on clock events.
Use sensitivity list for combinational, clock check for sequential.
Combinational has no memory; sequential stores state.
Remember: combinational = logic gates, sequential = flip-flops.

Full Transcript

This visual execution compares combinational and sequential processes in VHDL. The combinational process runs whenever inputs change, updating outputs immediately. The sequential process runs only on clock rising edges, updating outputs then. The execution table shows steps where inputs or clock trigger actions, and variable tracker shows how signals change over time. Key moments clarify why combinational outputs update immediately and sequential outputs wait for clock. The quiz tests understanding of when outputs change and how variables evolve. This helps beginners see the difference between immediate logic and clocked storage in hardware design.

Practice

1. Which statement best describes a combinational process in VHDL?

easy

A. It updates outputs only on clock edges.

B. It produces outputs based only on current inputs without memory.

C. It stores data over multiple clock cycles.

D. It requires a reset signal to function.

Solution

1. Step 1: Understand combinational logic behavior

   Combinational processes produce outputs immediately based on current inputs without storing any previous state.

2. Step 2: Compare with sequential behavior

   Sequential processes depend on clock edges and store data, unlike combinational ones.

3. Final Answer:

   It produces outputs based only on current inputs without memory. -> Option B

4. Quick Check:

   Combinational = current inputs only [OK]

Hint: Combinational = output changes instantly with inputs [OK]

Common Mistakes:

• Confusing combinational with sequential processes
• Thinking combinational processes use clocks
• Assuming combinational processes store data

2. Which of the following is the correct way to start a sequential process in VHDL?

easy

A. process(clk, reset) begin output <= input; end process;

B. process(a, b) begin output <= a and b; end process;

C. process(clk) begin if rising_edge(clk) then ... end if; end process;

D. process begin output <= input; end process;

Solution

1. Step 1: Identify sequential process syntax

   Sequential processes use a clock signal and check for clock edges, typically with if rising_edge(clk).

2. Step 2: Check options for clock edge usage

   Only process(clk) begin if rising_edge(clk) then ... end if; end process; uses rising_edge(clk) correctly to trigger sequential logic.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then ... end if; end process; -> Option C

4. Quick Check:

   Sequential process needs clock edge check [OK]

Hint: Sequential process always checks clock edge with rising_edge() [OK]

Common Mistakes:

• Omitting clock edge condition in sequential process
• Using input signals instead of clock in sensitivity list
• Writing combinational style inside sequential process

3. Given the following VHDL process, what is the output q when d = '1' and the clock rises?

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. q becomes '1' only at the rising edge of clk.

B. q never changes because d is not in sensitivity list.

C. q immediately becomes '1' when d changes.

D. q becomes '1' at the falling edge of clk.

Solution

1. Step 1: Analyze the process sensitivity and trigger

   The process triggers only on clk changes, specifically on rising edges.

2. Step 2: Understand when q updates

   q updates to d only at the rising edge of clk, not immediately when d changes.

3. Final Answer:

   q becomes '1' only at the rising edge of clk. -> Option A

4. Quick Check:

   Sequential output updates on clock edge [OK]

Hint: Sequential outputs update only on clock edges [OK]

Common Mistakes:

• Thinking output changes immediately with input
• Confusing sensitivity list with output update timing
• Assuming falling edge triggers update

4. Identify the error in this VHDL process intended as combinational logic:

process(clk)
begin
  output <= input1 and input2;
end process;

medium

A. The process must check for rising_edge(clk) to work correctly.

B. The process should not have any sensitivity list.

C. The output assignment should use <= only inside sequential processes.

D. The process sensitivity list should include input1 and input2, not clk.

Solution

1. Step 1: Understand combinational process sensitivity

   Combinational processes must list all inputs that affect outputs in the sensitivity list.

2. Step 2: Check the given sensitivity list

   The process sensitivity list incorrectly has only clk, which is unrelated to the inputs used.

3. Final Answer:

   The process sensitivity list should include input1 and input2, not clk. -> Option D

4. Quick Check:

   Combinational sensitivity = all inputs [OK]

Hint: Combinational process sensitivity must list all inputs [OK]

Common Mistakes:

• Using clock in combinational process sensitivity list
• Forgetting to include all inputs in sensitivity list
• Adding clock edge checks in combinational processes

5. You want to design a VHDL process that sets flag high immediately when input_signal is '1', but also resets flag to '0' on the rising edge of clk. Which approach correctly combines combinational and sequential behavior?

hard

A. Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag.

B. Use one process with sensitivity list (clk, input_signal) and inside check rising_edge(clk) to reset flag, else set flag based on input_signal.

C. Use only a sequential process triggered by clk to set and reset flag based on input_signal.

D. Use a combinational process triggered by clk to set flag and a sequential process triggered by input_signal to reset flag.

Solution

1. Step 1: Recognize need for immediate response and clocked reset

   Immediate set on input_signal='1' requires sensitivity to input_signal; clocked reset requires rising_edge(clk).

2. Step 2: Combine in single process

   Using separate processes avoids multiple driver conflicts: one combinational process sensitive to input_signal sets flag immediately, and a separate sequential process triggered by clk resets flag on rising edge.

3. Final Answer:

   Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag. -> Option A

4. Quick Check:

   Separate processes for immediate set and clocked reset [OK]

Hint: Separate combinational and sequential processes avoid conflicts [OK]

Common Mistakes:

• Using separate processes causing multiple driver conflicts
• Omitting input_signal from sensitivity list
• Using only sequential process with no immediate set