Combinational process vs sequential process in VHDL - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to define a combinational process that assigns output based on input.

VHDL

process(input_signal)
begin
  output_signal <= [1];
end process;

Drag options to blanks, or click blank then click option'

Arising_edge(clk)

Binput_signal

Cclk

Dwait

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edge detection in combinational process

Using wait statements inside combinational process

In a combinational process, output depends directly on input signals without clock edge detection.

2fill in blank

medium

Complete the code to define a sequential process triggered by clock's rising edge.

VHDL

process(clk)
begin
  if [1] then
    output_signal <= input_signal;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Arising_edge(clk)

Bfalling_edge(clk)

Cclk = '1'

Dclk = '0'

Attempts:

3 left

💡 Hint

Common Mistakes

Using falling_edge when rising_edge is expected

Using equality check instead of rising_edge function

Sequential processes use clock edges to update outputs synchronously.

3fill in blank

hard

Fix the error in the sequential process sensitivity list.

VHDL

process([1])
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bd

Cq

Dclk, d

Attempts:

3 left

💡 Hint

Common Mistakes

Including data signals in sensitivity list of sequential process

Leaving sensitivity list empty

Sequential processes should have only the clock signal in the sensitivity list.

4fill in blank

hard

Fill both blanks to create a combinational process with proper sensitivity list and assignment.

VHDL

process([1])
begin
  output_signal <= [2];
end process;

Drag options to blanks, or click blank then click option'

Ainput1, input2

Bclk

Cinput1 and input2

Dinput1 or input2

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock in sensitivity list for combinational process

Using logical AND instead of OR for output assignment

Combinational processes must list all inputs in sensitivity list and assign output based on logical OR of inputs.

5fill in blank

hard

Fill all three blanks to define a sequential process with reset and clock edge detection.

VHDL

process([1])
begin
  if [2] then
    output_signal <= (others => '0');
  elsif [3] then
    output_signal <= input_signal;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Breset = '1'

Crising_edge(clk)

Dreset = '0'

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting reset from sensitivity list

Checking clock edge before reset

Using incorrect reset condition

The process sensitivity list includes clock and reset. Reset condition is checked first, then clock edge for sequential update.

Practice

1. Which statement best describes a combinational process in VHDL?

easy

A. It updates outputs only on clock edges.

B. It produces outputs based only on current inputs without memory.

C. It stores data over multiple clock cycles.

D. It requires a reset signal to function.

Solution

1. Step 1: Understand combinational logic behavior

   Combinational processes produce outputs immediately based on current inputs without storing any previous state.

2. Step 2: Compare with sequential behavior

   Sequential processes depend on clock edges and store data, unlike combinational ones.

3. Final Answer:

   It produces outputs based only on current inputs without memory. -> Option B

4. Quick Check:

   Combinational = current inputs only [OK]

Hint: Combinational = output changes instantly with inputs [OK]

Common Mistakes:

• Confusing combinational with sequential processes
• Thinking combinational processes use clocks
• Assuming combinational processes store data

2. Which of the following is the correct way to start a sequential process in VHDL?

easy

A. process(clk, reset) begin output <= input; end process;

B. process(a, b) begin output <= a and b; end process;

C. process(clk) begin if rising_edge(clk) then ... end if; end process;

D. process begin output <= input; end process;

Solution

1. Step 1: Identify sequential process syntax

   Sequential processes use a clock signal and check for clock edges, typically with if rising_edge(clk).

2. Step 2: Check options for clock edge usage

   Only process(clk) begin if rising_edge(clk) then ... end if; end process; uses rising_edge(clk) correctly to trigger sequential logic.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then ... end if; end process; -> Option C

4. Quick Check:

   Sequential process needs clock edge check [OK]

Hint: Sequential process always checks clock edge with rising_edge() [OK]

Common Mistakes:

• Omitting clock edge condition in sequential process
• Using input signals instead of clock in sensitivity list
• Writing combinational style inside sequential process

3. Given the following VHDL process, what is the output q when d = '1' and the clock rises?

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. q becomes '1' only at the rising edge of clk.

B. q never changes because d is not in sensitivity list.

C. q immediately becomes '1' when d changes.

D. q becomes '1' at the falling edge of clk.

Solution

1. Step 1: Analyze the process sensitivity and trigger

   The process triggers only on clk changes, specifically on rising edges.

2. Step 2: Understand when q updates

   q updates to d only at the rising edge of clk, not immediately when d changes.

3. Final Answer:

   q becomes '1' only at the rising edge of clk. -> Option A

4. Quick Check:

   Sequential output updates on clock edge [OK]

Hint: Sequential outputs update only on clock edges [OK]

Common Mistakes:

• Thinking output changes immediately with input
• Confusing sensitivity list with output update timing
• Assuming falling edge triggers update

4. Identify the error in this VHDL process intended as combinational logic:

process(clk)
begin
  output <= input1 and input2;
end process;

medium

A. The process must check for rising_edge(clk) to work correctly.

B. The process should not have any sensitivity list.

C. The output assignment should use <= only inside sequential processes.

D. The process sensitivity list should include input1 and input2, not clk.

Solution

1. Step 1: Understand combinational process sensitivity

   Combinational processes must list all inputs that affect outputs in the sensitivity list.

2. Step 2: Check the given sensitivity list

   The process sensitivity list incorrectly has only clk, which is unrelated to the inputs used.

3. Final Answer:

   The process sensitivity list should include input1 and input2, not clk. -> Option D

4. Quick Check:

   Combinational sensitivity = all inputs [OK]

Hint: Combinational process sensitivity must list all inputs [OK]

Common Mistakes:

• Using clock in combinational process sensitivity list
• Forgetting to include all inputs in sensitivity list
• Adding clock edge checks in combinational processes

5. You want to design a VHDL process that sets flag high immediately when input_signal is '1', but also resets flag to '0' on the rising edge of clk. Which approach correctly combines combinational and sequential behavior?

hard

A. Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag.

B. Use one process with sensitivity list (clk, input_signal) and inside check rising_edge(clk) to reset flag, else set flag based on input_signal.

C. Use only a sequential process triggered by clk to set and reset flag based on input_signal.

D. Use a combinational process triggered by clk to set flag and a sequential process triggered by input_signal to reset flag.

Solution

1. Step 1: Recognize need for immediate response and clocked reset

   Immediate set on input_signal='1' requires sensitivity to input_signal; clocked reset requires rising_edge(clk).

2. Step 2: Combine in single process

   Using separate processes avoids multiple driver conflicts: one combinational process sensitive to input_signal sets flag immediately, and a separate sequential process triggered by clk resets flag on rising edge.

3. Final Answer:

   Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag. -> Option A

4. Quick Check:

   Separate processes for immediate set and clocked reset [OK]

Hint: Separate combinational and sequential processes avoid conflicts [OK]

Common Mistakes:

• Using separate processes causing multiple driver conflicts
• Omitting input_signal from sensitivity list
• Using only sequential process with no immediate set