Combinational process vs sequential process in VHDL - Hands-On Comparison

Combinational process vs sequential process in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. You need to understand how to write two types of processes: combinational and sequential. This will help you control how signals change in your circuit.

🎯 Goal: Build two VHDL processes: one combinational process that calculates the sum of two inputs, and one sequential process that stores the sum in a register on a clock edge.

📋 What You'll Learn

Create signals for inputs and outputs

Write a combinational process to add two inputs

Write a sequential process to store the result on clock rising edge

Print the stored result in simulation

💡 Why This Matters

🌍 Real World

Digital circuits often need to separate combinational logic (which calculates outputs immediately) from sequential logic (which stores values on clock edges). This project shows how to write both in VHDL.

💼 Career

Understanding combinational and sequential processes is essential for FPGA and ASIC design engineers who write hardware description languages like VHDL to build reliable digital systems.

1

Create input and output signals

Declare two input signals called a and b of type std_logic_vector(3 downto 0), and one output signal called sum of the same type inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_adder is
    Port (
        clk : in std_logic
    );
end simple_adder;

architecture Behavioral of simple_adder is
    signal a : std_logic_vector(3 downto 0);
    signal b : std_logic_vector(3 downto 0);
    signal sum : std_logic_vector(3 downto 0);
-- Your code here
begin

end Behavioral;

Hint

Signals are declared inside the architecture but before the begin keyword.

2

Add a combinational process to calculate sum

Write a combinational process called comb_process that uses a and b to calculate their sum and assign it to sum. Use process(a, b) and assign sum <= a + b; inside.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_adder is
    Port (
        clk : in std_logic
    );
end simple_adder;

architecture Behavioral of simple_adder is
    signal a : std_logic_vector(3 downto 0);
    signal b : std_logic_vector(3 downto 0);
    signal sum : std_logic_vector(3 downto 0);
begin
    process(a, b)
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use process(a, b) to make it combinational and convert vectors to unsigned for addition.

3

Add a sequential process to store sum on clock edge

Write a sequential process called seq_process triggered on the rising edge of clk. Inside, assign the value of sum to a new signal called stored_sum using a variable or signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity simple_adder is
    Port (
        clk : in std_logic
    );
end simple_adder;

architecture Behavioral of simple_adder is
    signal a : std_logic_vector(3 downto 0);
    signal b : std_logic_vector(3 downto 0);
    signal sum : std_logic_vector(3 downto 0);
    signal stored_sum : std_logic_vector(3 downto 0);
begin
    process(a, b)
    begin
        sum <= std_logic_vector(unsigned(a) + unsigned(b));
    end process;

    process(clk)
    begin
        if rising_edge(clk) then
            -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use if rising_edge(clk) then to detect clock edge and assign stored_sum <= sum;.

4

Print the stored sum value

Add a report statement inside the sequential process after storing stored_sum to print its value as a string using to_integer(unsigned(stored_sum)).

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity simple_adder is
    Port (
        clk : in std_logic
    );
end simple_adder;

architecture Behavioral of simple_adder is
    signal a : std_logic_vector(3 downto 0);
    signal b : std_logic_vector(3 downto 0);
    signal sum : std_logic_vector(3 downto 0);
    signal stored_sum : std_logic_vector(3 downto 0);
begin
    process(a, b)
    begin
        sum <= std_logic_vector(unsigned(a) + unsigned(b));
    end process;

    process(clk)
    begin
        if rising_edge(clk) then
            stored_sum <= sum;
            report "Stored sum is: " & integer'image(to_integer(unsigned(stored_sum)));
        end if;
    end process;
end Behavioral;

Hint

Use report with string concatenation and integer'image to print the stored sum.

Practice

1. Which statement best describes a combinational process in VHDL?

easy

A. It updates outputs only on clock edges.

B. It produces outputs based only on current inputs without memory.

C. It stores data over multiple clock cycles.

D. It requires a reset signal to function.

Solution

1. Step 1: Understand combinational logic behavior

   Combinational processes produce outputs immediately based on current inputs without storing any previous state.

2. Step 2: Compare with sequential behavior

   Sequential processes depend on clock edges and store data, unlike combinational ones.

3. Final Answer:

   It produces outputs based only on current inputs without memory. -> Option B

4. Quick Check:

   Combinational = current inputs only [OK]

Hint: Combinational = output changes instantly with inputs [OK]

Common Mistakes:

• Confusing combinational with sequential processes
• Thinking combinational processes use clocks
• Assuming combinational processes store data

2. Which of the following is the correct way to start a sequential process in VHDL?

easy

A. process(clk, reset) begin output <= input; end process;

B. process(a, b) begin output <= a and b; end process;

C. process(clk) begin if rising_edge(clk) then ... end if; end process;

D. process begin output <= input; end process;

Solution

1. Step 1: Identify sequential process syntax

   Sequential processes use a clock signal and check for clock edges, typically with if rising_edge(clk).

2. Step 2: Check options for clock edge usage

   Only process(clk) begin if rising_edge(clk) then ... end if; end process; uses rising_edge(clk) correctly to trigger sequential logic.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then ... end if; end process; -> Option C

4. Quick Check:

   Sequential process needs clock edge check [OK]

Hint: Sequential process always checks clock edge with rising_edge() [OK]

Common Mistakes:

• Omitting clock edge condition in sequential process
• Using input signals instead of clock in sensitivity list
• Writing combinational style inside sequential process

3. Given the following VHDL process, what is the output q when d = '1' and the clock rises?

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. q becomes '1' only at the rising edge of clk.

B. q never changes because d is not in sensitivity list.

C. q immediately becomes '1' when d changes.

D. q becomes '1' at the falling edge of clk.

Solution

1. Step 1: Analyze the process sensitivity and trigger

   The process triggers only on clk changes, specifically on rising edges.

2. Step 2: Understand when q updates

   q updates to d only at the rising edge of clk, not immediately when d changes.

3. Final Answer:

   q becomes '1' only at the rising edge of clk. -> Option A

4. Quick Check:

   Sequential output updates on clock edge [OK]

Hint: Sequential outputs update only on clock edges [OK]

Common Mistakes:

• Thinking output changes immediately with input
• Confusing sensitivity list with output update timing
• Assuming falling edge triggers update

4. Identify the error in this VHDL process intended as combinational logic:

process(clk)
begin
  output <= input1 and input2;
end process;

medium

A. The process must check for rising_edge(clk) to work correctly.

B. The process should not have any sensitivity list.

C. The output assignment should use <= only inside sequential processes.

D. The process sensitivity list should include input1 and input2, not clk.

Solution

1. Step 1: Understand combinational process sensitivity

   Combinational processes must list all inputs that affect outputs in the sensitivity list.

2. Step 2: Check the given sensitivity list

   The process sensitivity list incorrectly has only clk, which is unrelated to the inputs used.

3. Final Answer:

   The process sensitivity list should include input1 and input2, not clk. -> Option D

4. Quick Check:

   Combinational sensitivity = all inputs [OK]

Hint: Combinational process sensitivity must list all inputs [OK]

Common Mistakes:

• Using clock in combinational process sensitivity list
• Forgetting to include all inputs in sensitivity list
• Adding clock edge checks in combinational processes

5. You want to design a VHDL process that sets flag high immediately when input_signal is '1', but also resets flag to '0' on the rising edge of clk. Which approach correctly combines combinational and sequential behavior?

hard

A. Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag.

B. Use one process with sensitivity list (clk, input_signal) and inside check rising_edge(clk) to reset flag, else set flag based on input_signal.

C. Use only a sequential process triggered by clk to set and reset flag based on input_signal.

D. Use a combinational process triggered by clk to set flag and a sequential process triggered by input_signal to reset flag.

Solution

1. Step 1: Recognize need for immediate response and clocked reset

   Immediate set on input_signal='1' requires sensitivity to input_signal; clocked reset requires rising_edge(clk).

2. Step 2: Combine in single process

   Using separate processes avoids multiple driver conflicts: one combinational process sensitive to input_signal sets flag immediately, and a separate sequential process triggered by clk resets flag on rising edge.

3. Final Answer:

   Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag. -> Option A

4. Quick Check:

   Separate processes for immediate set and clocked reset [OK]

Hint: Separate combinational and sequential processes avoid conflicts [OK]

Common Mistakes:

• Using separate processes causing multiple driver conflicts
• Omitting input_signal from sensitivity list
• Using only sequential process with no immediate set