Combinational process vs sequential process in VHDL - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a combinational process

What is the output of the signal y after the following VHDL combinational process executes with inputs a = '1' and b = '0'?

VHDL

process(a, b) begin
  if a = '1' then
    y <= '1';
  else
    y <= b;
  end if;
end process;

A 'U' (undefined)

B '0'

C '1'

D No output change

💡 Hint

Remember that in a combinational process, output depends immediately on inputs.

Since a = '1', the condition if a = '1' is true, so y is assigned '1'.

❓ Predict Output

intermediate

Output behavior of a sequential process

Given the following VHDL sequential process triggered on the rising edge of clock clk, what is the value of q after the clock rises if d = '0' and q was previously '1'?

VHDL

process(clk) begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

A '0'

B No change until next clock

C 'U' (undefined)

D '1'

💡 Hint

Sequential processes update outputs only on clock edges.

At the rising edge of clk, q is assigned the value of d, which is '0'.

🧠 Conceptual

advanced

Difference in sensitivity lists

Which statement correctly describes the difference in sensitivity lists between combinational and sequential processes in VHDL?

A Sequential processes list all inputs; combinational processes list only the clock.

B Combinational processes must list all input signals in the sensitivity list; sequential processes typically only list the clock signal.

C Both combinational and sequential processes must list all signals they read in the sensitivity list.

D Sensitivity lists are not used in VHDL processes.

💡 Hint

Think about when each process should react to signal changes.

Combinational processes react to any input change, so all inputs must be in the sensitivity list. Sequential processes react only on clock edges, so only the clock is listed.

🔧 Debug

advanced

Identify the error in a combinational process

What error will occur with the following VHDL combinational process?

VHDL

process(a, b) begin
  if a = '1' then
    y <= '1';
  end if;
end process;

A Syntax error: missing else statement

B No error, process is correct

C Runtime error: signal y not initialized

D Latch inferred due to incomplete assignment of y

💡 Hint

Think about what happens to y when a is not '1'.

Because y is not assigned a value when a is not '1', the synthesizer infers a latch to hold the previous value.

❓ Predict Output

expert

Output of mixed combinational and sequential process

Consider the following VHDL code snippet. What is the value of z after the rising edge of clk if a = '1', b = '0', and z was initially '0'?

VHDL

process(a, b) begin
  if a = '1' then
    temp <= '1';
  else
    temp <= b;
  end if;
end process;

process(clk) begin
  if rising_edge(clk) then
    z <= temp;
  end if;
end process;

A '1'

B '0'

C 'U' (undefined)

D No change on z

💡 Hint

Remember that temp is updated combinationally and z updates on clock edge.

The combinational process sets temp to '1' because a = '1'. On the rising edge of clk, z takes the value of temp, which is '1'.

Practice

1. Which statement best describes a combinational process in VHDL?

easy

A. It updates outputs only on clock edges.

B. It produces outputs based only on current inputs without memory.

C. It stores data over multiple clock cycles.

D. It requires a reset signal to function.

Solution

1. Step 1: Understand combinational logic behavior

   Combinational processes produce outputs immediately based on current inputs without storing any previous state.

2. Step 2: Compare with sequential behavior

   Sequential processes depend on clock edges and store data, unlike combinational ones.

3. Final Answer:

   It produces outputs based only on current inputs without memory. -> Option B

4. Quick Check:

   Combinational = current inputs only [OK]

Hint: Combinational = output changes instantly with inputs [OK]

Common Mistakes:

• Confusing combinational with sequential processes
• Thinking combinational processes use clocks
• Assuming combinational processes store data

2. Which of the following is the correct way to start a sequential process in VHDL?

easy

A. process(clk, reset) begin output <= input; end process;

B. process(a, b) begin output <= a and b; end process;

C. process(clk) begin if rising_edge(clk) then ... end if; end process;

D. process begin output <= input; end process;

Solution

1. Step 1: Identify sequential process syntax

   Sequential processes use a clock signal and check for clock edges, typically with if rising_edge(clk).

2. Step 2: Check options for clock edge usage

   Only process(clk) begin if rising_edge(clk) then ... end if; end process; uses rising_edge(clk) correctly to trigger sequential logic.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then ... end if; end process; -> Option C

4. Quick Check:

   Sequential process needs clock edge check [OK]

Hint: Sequential process always checks clock edge with rising_edge() [OK]

Common Mistakes:

• Omitting clock edge condition in sequential process
• Using input signals instead of clock in sensitivity list
• Writing combinational style inside sequential process

3. Given the following VHDL process, what is the output q when d = '1' and the clock rises?

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. q becomes '1' only at the rising edge of clk.

B. q never changes because d is not in sensitivity list.

C. q immediately becomes '1' when d changes.

D. q becomes '1' at the falling edge of clk.

Solution

1. Step 1: Analyze the process sensitivity and trigger

   The process triggers only on clk changes, specifically on rising edges.

2. Step 2: Understand when q updates

   q updates to d only at the rising edge of clk, not immediately when d changes.

3. Final Answer:

   q becomes '1' only at the rising edge of clk. -> Option A

4. Quick Check:

   Sequential output updates on clock edge [OK]

Hint: Sequential outputs update only on clock edges [OK]

Common Mistakes:

• Thinking output changes immediately with input
• Confusing sensitivity list with output update timing
• Assuming falling edge triggers update

4. Identify the error in this VHDL process intended as combinational logic:

process(clk)
begin
  output <= input1 and input2;
end process;

medium

A. The process must check for rising_edge(clk) to work correctly.

B. The process should not have any sensitivity list.

C. The output assignment should use <= only inside sequential processes.

D. The process sensitivity list should include input1 and input2, not clk.

Solution

1. Step 1: Understand combinational process sensitivity

   Combinational processes must list all inputs that affect outputs in the sensitivity list.

2. Step 2: Check the given sensitivity list

   The process sensitivity list incorrectly has only clk, which is unrelated to the inputs used.

3. Final Answer:

   The process sensitivity list should include input1 and input2, not clk. -> Option D

4. Quick Check:

   Combinational sensitivity = all inputs [OK]

Hint: Combinational process sensitivity must list all inputs [OK]

Common Mistakes:

• Using clock in combinational process sensitivity list
• Forgetting to include all inputs in sensitivity list
• Adding clock edge checks in combinational processes

5. You want to design a VHDL process that sets flag high immediately when input_signal is '1', but also resets flag to '0' on the rising edge of clk. Which approach correctly combines combinational and sequential behavior?

hard

A. Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag.

B. Use one process with sensitivity list (clk, input_signal) and inside check rising_edge(clk) to reset flag, else set flag based on input_signal.

C. Use only a sequential process triggered by clk to set and reset flag based on input_signal.

D. Use a combinational process triggered by clk to set flag and a sequential process triggered by input_signal to reset flag.

Solution

1. Step 1: Recognize need for immediate response and clocked reset

   Immediate set on input_signal='1' requires sensitivity to input_signal; clocked reset requires rising_edge(clk).

2. Step 2: Combine in single process

   Using separate processes avoids multiple driver conflicts: one combinational process sensitive to input_signal sets flag immediately, and a separate sequential process triggered by clk resets flag on rising edge.

3. Final Answer:

   Use a combinational process for flag set with sensitivity input_signal, and a separate sequential process triggered by clk to reset flag. -> Option A

4. Quick Check:

   Separate processes for immediate set and clocked reset [OK]

Hint: Separate combinational and sequential processes avoid conflicts [OK]

Common Mistakes:

• Using separate processes causing multiple driver conflicts
• Omitting input_signal from sensitivity list
• Using only sequential process with no immediate set