SPI master controller in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the SPI clock signal.

VHDL

signal spi_clk : std_logic := '[1]';

Drag options to blanks, or click blank then click option'

A'1'

B'Z'

C'0'

D'X'

Attempts:

3 left

💡 Hint

Common Mistakes

Using '1' as initial value for spi_clk

Using 'Z' or 'X' which are undefined or high impedance states

The SPI clock signal is initialized to logic low, which is represented by '0' in VHDL.

2fill in blank

medium

Complete the code to define the SPI clock enable signal as active high.

VHDL

spi_clk_en <= [1];

Drag options to blanks, or click blank then click option'

A'0'

B'1'

Cspi_clk

Dnot spi_clk_en

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning '0' which disables the clock

Using expressions instead of a constant value

The SPI clock enable signal should be set to '1' to indicate it is active high.

3fill in blank

hard

Fix the error in the SPI clock process sensitivity list.

VHDL

process([1])
begin
  if rising_edge(clk) then
    spi_clk <= not spi_clk;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aspi_clk

Bspi_clk_en

Creset

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using spi_clk in sensitivity list causes no clock triggering

Using reset instead of clk

The process should be sensitive to the main clock signal 'clk' to toggle the SPI clock on its rising edge.

4fill in blank

hard

Fill both blanks to complete the SPI data shift register assignment and condition.

VHDL

if [1] = '1' then
  shift_reg <= shift_reg([2] downto 0) & mosi;
end if;

Drag options to blanks, or click blank then click option'

Aspi_clk_en

Bspi_clk

C7

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using spi_clk instead of spi_clk_en

Using 0 instead of 7 for the range

The shift register shifts data when the SPI clock enable is high, shifting bits down to index 7 (assuming 8-bit register).

5fill in blank

hard

Fill all three blanks to complete the SPI master controller state machine case statement.

VHDL

case state is
  when [1] =>
    if bit_count = [2] then
      state <= [3];
    end if;
  when others => null;
end case;

Drag options to blanks, or click blank then click option'

AIDLE

B7

CDONE

DSTART

Attempts:

3 left

💡 Hint

Common Mistakes

Using START instead of IDLE

Using 8 instead of 7 for bit_count

Transitioning to START instead of DONE

The state machine moves from IDLE state to DONE state after sending 8 bits (bit_count = 7).

Practice

1. What is the primary role of the SPI master controller in VHDL designs?

easy

A. To convert SPI signals into parallel data only

B. To act as a slave device responding to SPI commands

C. To generate random data for SPI devices

D. To control the clock, chip select, and data lines for SPI communication

Solution

1. Step 1: Understand SPI roles

   The SPI master controls communication timing and signals like clock and chip select.

2. Step 2: Identify controller function

   The master sends and receives data by managing these lines, unlike a slave which only responds.

3. Final Answer:

   To control the clock, chip select, and data lines for SPI communication -> Option D

4. Quick Check:

   SPI master controls clock, chip select, data lines [OK]

Hint: Master controls clock and chip select lines [OK]

Common Mistakes:

• Confusing master with slave device
• Thinking master only sends data without control
• Assuming master generates random data

2. Which VHDL statement correctly declares a 8-bit shift register signal for SPI data?

easy

A. signal shift_reg : integer range 0 to 255;

B. signal shift_reg : std_logic_vector(7 downto 0);

C. signal shift_reg : std_logic;

D. signal shift_reg : bit_vector(0 to 7);

Solution

1. Step 1: Identify correct data type for shift register

   Shift registers for SPI data use std_logic_vector for bit-wise operations.

2. Step 2: Check syntax and range

   std_logic_vector(7 downto 0) correctly defines 8 bits from MSB to LSB.

3. Final Answer:

   signal shift_reg : std_logic_vector(7 downto 0); -> Option B

4. Quick Check:

   Use std_logic_vector(7 downto 0) for 8-bit register [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of bit vector
• Using bit_vector which is less common
• Declaring single bit instead of vector

3. Given this VHDL process snippet for SPI clock generation:

process(clk)
begin
  if rising_edge(clk) then
    if clk_div = 1 then
      spi_clk <= not spi_clk;
      clk_div <= 0;
    else
      clk_div <= clk_div + 1;
    end if;
  end if;
end process;

What is the frequency relationship between spi_clk and clk?

medium

A. spi_clk frequency equals clk frequency

B. spi_clk frequency is double clk frequency

C. spi_clk frequency is half of clk frequency

D. spi_clk frequency is unrelated to clk frequency

Solution

1. Step 1: Analyze clock division logic

   clk_div toggles spi_clk every 2 rising edges of clk, flipping spi_clk once per two clk cycles.

2. Step 2: Determine frequency ratio

   Since spi_clk toggles every 2 clk cycles, its frequency is half of clk frequency.

3. Final Answer:

   spi_clk frequency is half of clk frequency -> Option C

4. Quick Check:

   spi_clk toggles every 2 clk cycles = half frequency [OK]

Hint: Toggle output every 2 input cycles halves frequency [OK]

Common Mistakes:

• Assuming frequencies are equal
• Thinking frequency doubles
• Ignoring clk_div counter effect

4. Identify the error in this SPI master controller state machine snippet:

type state_type is (IDLE, LOAD, TRANSFER);
signal state : state_type := IDLE;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= LOAD;
        end if;
      when LOAD =>
        state <= TRANSFER;
      when TRANSFER =>
        if bit_count = 8 then
          state <= IDLE;
        end if;
    end case;
  end if;
end process;

medium

A. bit_count is not reset, causing TRANSFER to never end

B. Missing default case in state machine

C. start signal is not checked in TRANSFER state

D. State transitions are missing LOAD to IDLE path

Solution

1. Step 1: Check state transitions and counters

   TRANSFER state depends on bit_count reaching 8 to return to IDLE.

2. Step 2: Identify missing reset of bit_count

   If bit_count is never reset to 0, it may never reach 8, so TRANSFER state loops indefinitely.

3. Final Answer:

   bit_count is not reset, causing TRANSFER to never end -> Option A

4. Quick Check:

   bit_count reset missing = infinite TRANSFER [OK]

Hint: Always reset counters to avoid infinite states [OK]

Common Mistakes:

• Ignoring counter reset logic
• Expecting default case is mandatory
• Confusing start signal usage

5. You want to extend an SPI master controller to support variable data widths (4 to 16 bits). Which VHDL approach best handles this requirement?

hard

A. Use a generic parameter for data width and adjust shift register size accordingly

B. Hardcode shift register to 16 bits and ignore unused bits

C. Create separate modules for each data width and select at compile time

D. Use integer counters only without shift registers

Solution

1. Step 1: Understand variable data width needs

   Supporting 4 to 16 bits requires flexible register size and control logic.

2. Step 2: Use generics for flexibility

   Generics allow parameterizing data width at compile time, adjusting shift register size dynamically.

3. Step 3: Evaluate other options

   Hardcoding wastes resources; separate modules increase complexity; counters alone can't shift data.

4. Final Answer:

   Use a generic parameter for data width and adjust shift register size accordingly -> Option A

5. Quick Check:

   Generics enable flexible data width in VHDL [OK]

Hint: Use generics to set data width flexibly [OK]

Common Mistakes:

• Hardcoding fixed sizes wastes resources
• Creating many modules complicates design
• Ignoring shift register role in data transfer