SPI master controller in VHDL - Mini Project: Build & Apply

SPI Master Controller

📖 Scenario: You are designing a simple SPI (Serial Peripheral Interface) master controller in VHDL. SPI is a common way for microcontrollers to communicate with sensors and other devices using a few wires.This project will guide you through creating a basic SPI master that can send 8-bit data to a slave device.

🎯 Goal: Build a VHDL SPI master controller that sends an 8-bit data byte over SPI with proper clock and chip select signals.

📋 What You'll Learn

Create signals for SPI clock (SCLK), Master Out Slave In (MOSI), and Chip Select (CS).

Use a clock divider to generate the SPI clock from the system clock.

Implement a shift register to send 8 bits of data serially on MOSI.

Control the CS signal to enable communication during data transfer.

💡 Why This Matters

🌍 Real World

SPI is widely used to connect microcontrollers to sensors, memory chips, and other peripherals in embedded systems.

💼 Career

Understanding SPI and how to implement it in hardware description languages like VHDL is valuable for FPGA and embedded systems engineers.

1

Create SPI signals and data register

Create signals called SCLK, MOSI, and CS as type std_logic. Also create a signal called data_to_send of type std_logic_vector(7 downto 0) and initialize it with "10101010".

VHDL

-- Declare SPI signals and data register
-- Your code here

Hint

Use signal keyword to declare signals. Initialize CS to '1' (inactive) and data_to_send with the exact bit pattern.

2

Create clock divider for SPI clock

Create a signal called clk_div of type integer range 0 to 3 initialized to 0. Then create a process triggered on the rising edge of clk that increments clk_div by 1 and resets it to 0 when it reaches 3. Toggle SCLK when clk_div is 0.

VHDL

signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal CS : std_logic := '1';
signal data_to_send : std_logic_vector(7 downto 0) := "10101010";
-- Create clk_div signal and clock divider process
-- Your code here

Hint

Use a process sensitive to clk. Increment clk_div each clock cycle and toggle SCLK when clk_div resets.

3

Implement shift register to send data on MOSI

Create a signal called bit_counter of type integer range 0 to 7 initialized to 7. Create a signal called shift_reg of type std_logic_vector(7 downto 0) initialized with data_to_send. In a process triggered on the rising edge of SCLK, if bit_counter >= 0, assign MOSI to shift_reg(bit_counter), then decrement bit_counter by 1.

VHDL

signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal CS : std_logic := '1';
signal data_to_send : std_logic_vector(7 downto 0) := "10101010";
signal clk_div : integer range 0 to 3 := 0;
-- Create bit_counter and shift_reg signals
signal bit_counter : integer range 0 to 7 := 7;
signal shift_reg : std_logic_vector(7 downto 0) := data_to_send;

process(clk)
begin
    if rising_edge(clk) then
        if clk_div = 3 then
            clk_div <= 0;
            SCLK <= not SCLK;
        else
            clk_div <= clk_div + 1;
        end if;
    end if;
end process;

-- Create process triggered on rising edge of SCLK to shift data
-- Your code here

Hint

Use a process sensitive to SCLK. On each rising edge, output the current bit on MOSI and decrease bit_counter.

4

Control chip select and print SPI signals

Set CS to '0' when bit_counter <= 7 and >= 0 to enable the slave device during transmission. Set CS to '1' otherwise. Add a process triggered on the rising edge of clk that prints the values of CS, SCLK, and MOSI using report statements.

VHDL

signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal CS : std_logic := '1';
signal data_to_send : std_logic_vector(7 downto 0) := "10101010";
signal clk_div : integer range 0 to 3 := 0;
signal bit_counter : integer range 0 to 7 := 7;
signal shift_reg : std_logic_vector(7 downto 0) := data_to_send;

process(clk)
begin
    if rising_edge(clk) then
        if clk_div = 3 then
            clk_div = 0 then
            MOSI <= shift_reg(bit_counter);
            bit_counter <= bit_counter - 1;
        end if;
    end if;
end process;

-- Add a process to print CS, SCLK, and MOSI signals
-- Your code here

Hint

Set CS low during transmission and high otherwise. Use report statements inside a clocked process to print signal values.

Practice

1. What is the primary role of the SPI master controller in VHDL designs?

easy

A. To convert SPI signals into parallel data only

B. To act as a slave device responding to SPI commands

C. To generate random data for SPI devices

D. To control the clock, chip select, and data lines for SPI communication

Solution

1. Step 1: Understand SPI roles

   The SPI master controls communication timing and signals like clock and chip select.

2. Step 2: Identify controller function

   The master sends and receives data by managing these lines, unlike a slave which only responds.

3. Final Answer:

   To control the clock, chip select, and data lines for SPI communication -> Option D

4. Quick Check:

   SPI master controls clock, chip select, data lines [OK]

Hint: Master controls clock and chip select lines [OK]

Common Mistakes:

• Confusing master with slave device
• Thinking master only sends data without control
• Assuming master generates random data

2. Which VHDL statement correctly declares a 8-bit shift register signal for SPI data?

easy

A. signal shift_reg : integer range 0 to 255;

B. signal shift_reg : std_logic_vector(7 downto 0);

C. signal shift_reg : std_logic;

D. signal shift_reg : bit_vector(0 to 7);

Solution

1. Step 1: Identify correct data type for shift register

   Shift registers for SPI data use std_logic_vector for bit-wise operations.

2. Step 2: Check syntax and range

   std_logic_vector(7 downto 0) correctly defines 8 bits from MSB to LSB.

3. Final Answer:

   signal shift_reg : std_logic_vector(7 downto 0); -> Option B

4. Quick Check:

   Use std_logic_vector(7 downto 0) for 8-bit register [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of bit vector
• Using bit_vector which is less common
• Declaring single bit instead of vector

3. Given this VHDL process snippet for SPI clock generation:

process(clk)
begin
  if rising_edge(clk) then
    if clk_div = 1 then
      spi_clk <= not spi_clk;
      clk_div <= 0;
    else
      clk_div <= clk_div + 1;
    end if;
  end if;
end process;

What is the frequency relationship between spi_clk and clk?

medium

A. spi_clk frequency equals clk frequency

B. spi_clk frequency is double clk frequency

C. spi_clk frequency is half of clk frequency

D. spi_clk frequency is unrelated to clk frequency

Solution

1. Step 1: Analyze clock division logic

   clk_div toggles spi_clk every 2 rising edges of clk, flipping spi_clk once per two clk cycles.

2. Step 2: Determine frequency ratio

   Since spi_clk toggles every 2 clk cycles, its frequency is half of clk frequency.

3. Final Answer:

   spi_clk frequency is half of clk frequency -> Option C

4. Quick Check:

   spi_clk toggles every 2 clk cycles = half frequency [OK]

Hint: Toggle output every 2 input cycles halves frequency [OK]

Common Mistakes:

• Assuming frequencies are equal
• Thinking frequency doubles
• Ignoring clk_div counter effect

4. Identify the error in this SPI master controller state machine snippet:

type state_type is (IDLE, LOAD, TRANSFER);
signal state : state_type := IDLE;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= LOAD;
        end if;
      when LOAD =>
        state <= TRANSFER;
      when TRANSFER =>
        if bit_count = 8 then
          state <= IDLE;
        end if;
    end case;
  end if;
end process;

medium

A. bit_count is not reset, causing TRANSFER to never end

B. Missing default case in state machine

C. start signal is not checked in TRANSFER state

D. State transitions are missing LOAD to IDLE path

Solution

1. Step 1: Check state transitions and counters

   TRANSFER state depends on bit_count reaching 8 to return to IDLE.

2. Step 2: Identify missing reset of bit_count

   If bit_count is never reset to 0, it may never reach 8, so TRANSFER state loops indefinitely.

3. Final Answer:

   bit_count is not reset, causing TRANSFER to never end -> Option A

4. Quick Check:

   bit_count reset missing = infinite TRANSFER [OK]

Hint: Always reset counters to avoid infinite states [OK]

Common Mistakes:

• Ignoring counter reset logic
• Expecting default case is mandatory
• Confusing start signal usage

5. You want to extend an SPI master controller to support variable data widths (4 to 16 bits). Which VHDL approach best handles this requirement?

hard

A. Use a generic parameter for data width and adjust shift register size accordingly

B. Hardcode shift register to 16 bits and ignore unused bits

C. Create separate modules for each data width and select at compile time

D. Use integer counters only without shift registers

Solution

1. Step 1: Understand variable data width needs

   Supporting 4 to 16 bits requires flexible register size and control logic.

2. Step 2: Use generics for flexibility

   Generics allow parameterizing data width at compile time, adjusting shift register size dynamically.

3. Step 3: Evaluate other options

   Hardcoding wastes resources; separate modules increase complexity; counters alone can't shift data.

4. Final Answer:

   Use a generic parameter for data width and adjust shift register size accordingly -> Option A

5. Quick Check:

   Generics enable flexible data width in VHDL [OK]

Hint: Use generics to set data width flexibly [OK]

Common Mistakes:

• Hardcoding fixed sizes wastes resources
• Creating many modules complicates design
• Ignoring shift register role in data transfer