SPI master controller in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

SPI Master Clock Generation Output

What is the output frequency of the SPI clock (SCLK) generated by this VHDL process if the input clock is 50 MHz and the clock divider is set to 4?

process(clk)
begin
  if rising_edge(clk) then
    if counter = (divider / 2) - 1 then
      sclk <= not sclk;
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

VHDL

signal sclk : std_logic := '0';
signal counter : integer := 0;
constant divider : integer := 4;
-- clk frequency = 50 MHz

A 50 MHz

B 25 MHz

C 12.5 MHz

D 6.25 MHz

💡 Hint

The SPI clock toggles every half period of the divided clock.

The divider divides the input clock by 4. The sclk toggles every (divider/2) cycles, so the output frequency is 50 MHz / 4 = 12.5 MHz.

❓ Predict Output

intermediate

SPI Master Data Shift Output

Given the following VHDL snippet for shifting out data MSB first on MOSI line, what is the value of MOSI after 3 clock cycles if data_out is "10110011" and shift_reg is initialized with data_out?

process(clk)
begin
  if rising_edge(clk) then
    if start = '1' then
      shift_reg <= data_out;
    elsif shifting = '1' then
      MOSI <= shift_reg(7);
      shift_reg <= shift_reg(6 downto 0) & '0';
    end if;
  end if;
end process;

VHDL

signal shift_reg : std_logic_vector(7 downto 0);
signal MOSI : std_logic;
signal data_out : std_logic_vector(7 downto 0) := "10110011";
signal start : std_logic := '1';
signal shifting : std_logic := '0';

A '1'

B '0'

C 'X' (undefined)

D 'Z' (high impedance)

💡 Hint

Look at the MSB of data_out and how it shifts out.

The MSB of data_out is '1'. After loading shift_reg, the first MOSI output is '1'. After 3 shifts, MOSI outputs the bits in order: '1', '0', '1'. After the third clock cycle, MOSI is '1'.

🔧 Debug

advanced

Identify the Error in SPI Chip Select Logic

What error will this VHDL code cause when trying to control the SPI chip select (CS) signal?

process(clk)
begin
  if rising_edge(clk) then
    if start = '1' then
      CS <= '0';
    else
      CS <= '1';
    end if;
  end if;
end process;

CS <= '1';

VHDL

signal CS : std_logic := '1';
signal start : std_logic;

A No error; CS works as expected

B CS will always be '1' ignoring the process

C CS will toggle randomly causing SPI errors

D Compilation error due to multiple drivers on CS signal

💡 Hint

Check if CS is assigned in multiple places.

CS is assigned inside the process and also outside it concurrently. This creates multiple drivers on the same signal, causing a compilation error.

📝 Syntax

advanced

Syntax Error in SPI State Machine

Which option contains the correct syntax for a VHDL case statement inside a process handling SPI states?

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        CS <= '1';
      when TRANSFER =>
        CS <= '0';
      when others =>
        CS <= '1';
    end case;
  end if;
end process;

A

case state is
  when IDLE => CS <= '1';
  when TRANSFER => CS <= '0';
  when others => CS <= '1';
end case;

B

case state of
  when IDLE => CS <= '1';
  when TRANSFER => CS <= '0';
  when others => CS <= '1';
end case;

C

case state is
  when IDLE : CS <= '1';
  when TRANSFER : CS <= '0';
  when others : CS <= '1';
end case;

D

case state of
  when IDLE : CS <= '1';
  when TRANSFER : CS <= '0';
  when others : CS <= '1';
end case;

💡 Hint

VHDL case statements use 'case ... is' and 'when ... =>' syntax.

The correct syntax for a VHDL case statement uses 'case ... is' and 'when ... =>'. Using 'case ... of' or ':' instead of '=>' causes syntax errors.

🚀 Application

expert

Calculate Total SPI Transfer Time

An SPI master controller runs with a 100 MHz system clock. It divides this clock by 8 to generate the SPI clock (SCLK). It transfers 16 bits per transaction. What is the total time in microseconds to complete one SPI transfer?

Assume the SPI clock toggles every (divider/2) cycles and each bit requires one full SCLK cycle.

A 0.8 microseconds

B 1.28 microseconds

C 2.56 microseconds

D 0.16 microseconds

💡 Hint

Calculate SCLK frequency first, then multiply by bits and clock period.

System clock is 100 MHz. Divider is 8, so SCLK frequency = 100 MHz / 8 = 12.5 MHz. One SCLK period = 1 / 12.5 MHz = 0.08 microseconds. For 16 bits, total time = 16 * 0.08 = 1.28 microseconds.

Practice

1. What is the primary role of the SPI master controller in VHDL designs?

easy

A. To convert SPI signals into parallel data only

B. To act as a slave device responding to SPI commands

C. To generate random data for SPI devices

D. To control the clock, chip select, and data lines for SPI communication

Solution

1. Step 1: Understand SPI roles

   The SPI master controls communication timing and signals like clock and chip select.

2. Step 2: Identify controller function

   The master sends and receives data by managing these lines, unlike a slave which only responds.

3. Final Answer:

   To control the clock, chip select, and data lines for SPI communication -> Option D

4. Quick Check:

   SPI master controls clock, chip select, data lines [OK]

Hint: Master controls clock and chip select lines [OK]

Common Mistakes:

• Confusing master with slave device
• Thinking master only sends data without control
• Assuming master generates random data

2. Which VHDL statement correctly declares a 8-bit shift register signal for SPI data?

easy

A. signal shift_reg : integer range 0 to 255;

B. signal shift_reg : std_logic_vector(7 downto 0);

C. signal shift_reg : std_logic;

D. signal shift_reg : bit_vector(0 to 7);

Solution

1. Step 1: Identify correct data type for shift register

   Shift registers for SPI data use std_logic_vector for bit-wise operations.

2. Step 2: Check syntax and range

   std_logic_vector(7 downto 0) correctly defines 8 bits from MSB to LSB.

3. Final Answer:

   signal shift_reg : std_logic_vector(7 downto 0); -> Option B

4. Quick Check:

   Use std_logic_vector(7 downto 0) for 8-bit register [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of bit vector
• Using bit_vector which is less common
• Declaring single bit instead of vector

3. Given this VHDL process snippet for SPI clock generation:

process(clk)
begin
  if rising_edge(clk) then
    if clk_div = 1 then
      spi_clk <= not spi_clk;
      clk_div <= 0;
    else
      clk_div <= clk_div + 1;
    end if;
  end if;
end process;

What is the frequency relationship between spi_clk and clk?

medium

A. spi_clk frequency equals clk frequency

B. spi_clk frequency is double clk frequency

C. spi_clk frequency is half of clk frequency

D. spi_clk frequency is unrelated to clk frequency

Solution

1. Step 1: Analyze clock division logic

   clk_div toggles spi_clk every 2 rising edges of clk, flipping spi_clk once per two clk cycles.

2. Step 2: Determine frequency ratio

   Since spi_clk toggles every 2 clk cycles, its frequency is half of clk frequency.

3. Final Answer:

   spi_clk frequency is half of clk frequency -> Option C

4. Quick Check:

   spi_clk toggles every 2 clk cycles = half frequency [OK]

Hint: Toggle output every 2 input cycles halves frequency [OK]

Common Mistakes:

• Assuming frequencies are equal
• Thinking frequency doubles
• Ignoring clk_div counter effect

4. Identify the error in this SPI master controller state machine snippet:

type state_type is (IDLE, LOAD, TRANSFER);
signal state : state_type := IDLE;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= LOAD;
        end if;
      when LOAD =>
        state <= TRANSFER;
      when TRANSFER =>
        if bit_count = 8 then
          state <= IDLE;
        end if;
    end case;
  end if;
end process;

medium

A. bit_count is not reset, causing TRANSFER to never end

B. Missing default case in state machine

C. start signal is not checked in TRANSFER state

D. State transitions are missing LOAD to IDLE path

Solution

1. Step 1: Check state transitions and counters

   TRANSFER state depends on bit_count reaching 8 to return to IDLE.

2. Step 2: Identify missing reset of bit_count

   If bit_count is never reset to 0, it may never reach 8, so TRANSFER state loops indefinitely.

3. Final Answer:

   bit_count is not reset, causing TRANSFER to never end -> Option A

4. Quick Check:

   bit_count reset missing = infinite TRANSFER [OK]

Hint: Always reset counters to avoid infinite states [OK]

Common Mistakes:

• Ignoring counter reset logic
• Expecting default case is mandatory
• Confusing start signal usage

5. You want to extend an SPI master controller to support variable data widths (4 to 16 bits). Which VHDL approach best handles this requirement?

hard

A. Use a generic parameter for data width and adjust shift register size accordingly

B. Hardcode shift register to 16 bits and ignore unused bits

C. Create separate modules for each data width and select at compile time

D. Use integer counters only without shift registers

Solution

1. Step 1: Understand variable data width needs

   Supporting 4 to 16 bits requires flexible register size and control logic.

2. Step 2: Use generics for flexibility

   Generics allow parameterizing data width at compile time, adjusting shift register size dynamically.

3. Step 3: Evaluate other options

   Hardcoding wastes resources; separate modules increase complexity; counters alone can't shift data.

4. Final Answer:

   Use a generic parameter for data width and adjust shift register size accordingly -> Option A

5. Quick Check:

   Generics enable flexible data width in VHDL [OK]

Hint: Use generics to set data width flexibly [OK]

Common Mistakes:

• Hardcoding fixed sizes wastes resources
• Creating many modules complicates design
• Ignoring shift register role in data transfer