Resource inference rules in VHDL - Step-by-Step Execution

Concept Flow - Resource inference rules

Start: VHDL code with signals and processes

↓

Analyze signal assignments

↓

Check for combinational or sequential logic

↓

Apply inference rules

↓

Infer combinational

↓

Map to hardware resource

↓

Generate netlist

The VHDL compiler analyzes signal assignments and processes, applies inference rules to decide hardware resources, then maps logic to hardware components.

Execution Sample

VHDL

process(a, b)
begin
  y <= a and b;
end process;

This process infers a combinational AND gate from signals a and b to output y.

Execution Table

Step	Action	Signal/Process	Inference	Hardware Resource
1	Detect process sensitivity list	process(a, b)	Combinational logic detected	N/A
2	Analyze assignment	y <= a and b;	AND operation between a and b	N/A
3	Apply inference rule	AND operation	Infer combinational AND gate	AND gate
4	Map to hardware	AND gate	Map to physical AND gate resource	AND gate instantiated
5	End process analysis	process(a, b)	Process fully inferred	Hardware resource assigned

💡 All signal assignments analyzed and mapped to hardware resources

Variable Tracker

Variable	Start	After Step 2	After Step 3	Final
a	input signal	input signal	input signal	input signal
b	input signal	input signal	input signal	input signal
y	unassigned	assigned a AND b	inferred as output of AND gate	output of AND gate

Key Moments - 2 Insights

Why does the compiler infer an AND gate instead of a flip-flop?

Because the process sensitivity list includes signals a and b only, and the assignment is direct without clock edges, the inference rule detects combinational logic (see execution_table step 1 and 3).

What happens if the process uses a clock signal in the sensitivity list?

The inference rules detect sequential logic and infer flip-flops or registers instead of combinational gates (not shown here but would change step 1 and 3).

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what hardware resource is inferred?

A OR gate

B Flip-flop

C AND gate

D Multiplexer

💡 Hint

Refer to the 'Hardware Resource' column at step 3 in execution_table

At which step does the compiler map the logic to a physical hardware resource?

A Step 4

B Step 2

C Step 3

D Step 5

💡 Hint

Check the 'Action' and 'Hardware Resource' columns in execution_table for mapping step

If the process sensitivity list included a clock signal, how would the inference change?

A Infer combinational logic

B Infer sequential logic (flip-flops)

C No inference possible

D Infer memory blocks

💡 Hint

See key_moments explanation about clock signal effect on inference

Concept Snapshot

Resource inference rules in VHDL:
- Analyze signal assignments and process sensitivity
- Detect combinational vs sequential logic
- Infer hardware resources (AND gate, flip-flop, etc.)
- Map inferred logic to physical hardware
- Enables automatic hardware generation from code

Full Transcript

In VHDL, resource inference rules help the compiler decide what hardware to create from your code. It looks at signal assignments and process sensitivity lists to tell if the logic is combinational or sequential. For example, a process sensitive to signals a and b with assignment y <= a and b; infers an AND gate. If a clock is in the sensitivity list, it infers flip-flops. The compiler then maps these inferred components to actual hardware resources. This process is automatic and helps turn your VHDL code into real circuits.

Practice

1. Which VHDL construct typically causes the compiler to infer a register (flip-flop)?

easy

A. A clocked process with a rising_edge(clock) condition

B. A simple concurrent signal assignment

C. A combinational process without clock sensitivity

D. A constant declaration

Solution

1. Step 1: Understand what infers registers

   Registers (flip-flops) are inferred when signals are assigned inside a process triggered by a clock edge, such as rising_edge(clock).

2. Step 2: Identify the correct construct

   A clocked process with rising_edge(clock) matches this condition, so it infers registers.

3. Final Answer:

   A clocked process with a rising_edge(clock) condition -> Option A

4. Quick Check:

   Clocked process = register inference [OK]

Hint: Registers come from clocked processes with edge checks [OK]

Common Mistakes:

• Confusing combinational assignments with registers
• Thinking constants infer registers
• Ignoring the clock edge condition

2. Which of the following VHDL code snippets correctly infers combinational logic?

easy

A. q <= a and b;

B. signal r : std_logic_vector(3 downto 0);

C. constant c : integer := 5;

D. process(clk) begin if rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify combinational logic inference

   Combinational logic is inferred from concurrent signal assignments or processes without clock edges.

2. Step 2: Check each option

   q <= a and b; is a concurrent assignment using logical AND, which infers combinational logic.

3. Final Answer:

   q <= a and b; -> Option A

4. Quick Check:

   Concurrent assignment = combinational logic [OK]

Hint: Combinational logic comes from simple concurrent assignments [OK]

Common Mistakes:

• Choosing clocked processes for combinational logic
• Confusing constants or signals with logic inference
• Ignoring the absence of clock edges

3. Given the following VHDL code, what hardware resource is inferred?

process(clk, a, b)
begin
  if rising_edge(clk) then
    q <= a or b;
  end if;
end process;

medium

A. Combinational logic only

B. Register (flip-flop) with combinational logic inside

C. Constant value

D. Latch

Solution

1. Step 1: Analyze the process sensitivity and clock usage

   The process is sensitive to clk, a, and b, but the assignment happens only on rising_edge(clk), indicating a clocked process.

2. Step 2: Determine inferred hardware

   Because the assignment is inside a clock edge condition, a register (flip-flop) is inferred. The expression 'a or b' is combinational logic feeding the register input.

3. Final Answer:

   Register (flip-flop) with combinational logic inside -> Option B

4. Quick Check:

   Clock edge + logic = register with combinational input [OK]

Hint: Clock edge inside process means register inferred [OK]

Common Mistakes:

• Ignoring the clock edge and thinking it's pure combinational
• Confusing latch with register
• Assuming constants are inferred

4. Identify the error in this VHDL code that prevents correct resource inference:

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

medium

A. Signal q is not declared

B. Process sensitivity list is empty

C. Missing rising_edge(clk) condition for clocked process

D. Constant d is used instead of signal

Solution

1. Step 1: Check clock condition usage

   The process uses 'if clk = '1'' instead of 'if rising_edge(clk)', which is the standard way to infer registers.

2. Step 2: Understand impact on resource inference

   Without rising_edge(clk), the compiler may infer a latch or incorrect hardware instead of a register.

3. Final Answer:

   Missing rising_edge(clk) condition for clocked process -> Option C

4. Quick Check:

   Use rising_edge(clk) for registers [OK]

Hint: Always use rising_edge(clk) for registers [OK]

Common Mistakes:

• Using level-sensitive clock check instead of edge
• Ignoring sensitivity list correctness
• Assuming signal declarations cause inference errors

5. You want to infer a 4-bit register with asynchronous reset in VHDL. Which code snippet correctly follows resource inference rules?

hard

A. process(reset) begin if reset = '1' then q <= (others => '0'); end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); else q <= d; end if; end if; end process;

C. q <= d when reset = '0' else (others => '0');

D. process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify asynchronous reset structure

   An asynchronous reset requires the reset signal in the sensitivity list and a separate if condition before the clock edge check.

2. Step 2: Check each option for correct inference

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; has reset and clk in sensitivity list, checks reset first, then rising_edge(clk), correctly inferring a register with async reset.

3. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; -> Option D

4. Quick Check:

   Async reset in sensitivity + if reset first = correct [OK]

Hint: Async reset must be checked before clock edge in process [OK]

Common Mistakes:

• Placing reset check inside clock edge condition (sync reset)
• Missing reset in sensitivity list for async reset
• Using conditional assignments outside process for registers