Resource inference rules in VHDL - Mini Project: Build & Apply

Resource Inference Rules in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. You want to understand how VHDL infers hardware resources like flip-flops and combinational logic from your code.

🎯 Goal: Build a VHDL design that uses resource inference rules to create flip-flops and combinational logic automatically. You will write a simple process with signals and observe how VHDL infers registers and logic gates.

📋 What You'll Learn

Create a signal to hold a 4-bit input value

Create a clock signal for synchronous logic

Write a process that infers flip-flops using the clock

Assign combinational logic using signal assignments

Print the output signals to verify the design

💡 Why This Matters

🌍 Real World

Digital designers use resource inference rules in VHDL to write code that automatically creates hardware components like registers and logic gates without manually instantiating them.

💼 Career

Understanding resource inference is essential for FPGA and ASIC design engineers to write efficient and synthesizable VHDL code.

1

DATA SETUP: Declare signals for input and clock

Declare a 4-bit signal called input_signal initialized to "0000" and a signal called clk of type std_logic initialized to '0'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity resource_inference is
end resource_inference;

architecture Behavioral of resource_inference is
    -- Your code here
begin
end Behavioral;

Hint

Use signal keyword to declare signals inside the architecture.

2

CONFIGURATION: Add a signal to hold registered output

Declare a signal called registered_output of type std_logic_vector(3 downto 0) initialized to "0000" to hold the registered value.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity resource_inference is
end resource_inference;

architecture Behavioral of resource_inference is
    signal input_signal : std_logic_vector(3 downto 0) := "0000";
    signal clk : std_logic := '0';
    signal registered_output : std_logic_vector(3 downto 0) := "0000";
    
    -- Your code here
begin
end Behavioral;

Hint

Declare the new signal just like the others inside the architecture.

3

CORE LOGIC: Write a process to infer flip-flops

Write a process called register_process that triggers on the rising edge of clk and assigns input_signal to registered_output inside the process.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity resource_inference is
end resource_inference;

architecture Behavioral of resource_inference is
    signal input_signal : std_logic_vector(3 downto 0) := "0000";
    signal clk : std_logic := '0';
    signal registered_output : std_logic_vector(3 downto 0) := "0000";
begin
    process(clk)
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use process(clk) and if rising_edge(clk) then to create synchronous logic.

4

OUTPUT: Assign combinational logic and print outputs

Assign a signal called output_signal as the bitwise NOT of registered_output. Then write a simple testbench process that prints registered_output and output_signal values.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity resource_inference is
end resource_inference;

architecture Behavioral of resource_inference is
    signal input_signal : std_logic_vector(3 downto 0) := "0000";
    signal clk : std_logic := '0';
    signal registered_output : std_logic_vector(3 downto 0) := "0000";
    signal output_signal : std_logic_vector(3 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            registered_output <= input_signal;
        end if;
    end process;
    output_signal <= not registered_output;
    -- Your code here
end Behavioral;

Hint

Use output_signal <= not registered_output; for combinational logic. Use a process with write and writeline to print signals.

Practice

1. Which VHDL construct typically causes the compiler to infer a register (flip-flop)?

easy

A. A clocked process with a rising_edge(clock) condition

B. A simple concurrent signal assignment

C. A combinational process without clock sensitivity

D. A constant declaration

Solution

1. Step 1: Understand what infers registers

   Registers (flip-flops) are inferred when signals are assigned inside a process triggered by a clock edge, such as rising_edge(clock).

2. Step 2: Identify the correct construct

   A clocked process with rising_edge(clock) matches this condition, so it infers registers.

3. Final Answer:

   A clocked process with a rising_edge(clock) condition -> Option A

4. Quick Check:

   Clocked process = register inference [OK]

Hint: Registers come from clocked processes with edge checks [OK]

Common Mistakes:

• Confusing combinational assignments with registers
• Thinking constants infer registers
• Ignoring the clock edge condition

2. Which of the following VHDL code snippets correctly infers combinational logic?

easy

A. q <= a and b;

B. signal r : std_logic_vector(3 downto 0);

C. constant c : integer := 5;

D. process(clk) begin if rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify combinational logic inference

   Combinational logic is inferred from concurrent signal assignments or processes without clock edges.

2. Step 2: Check each option

   q <= a and b; is a concurrent assignment using logical AND, which infers combinational logic.

3. Final Answer:

   q <= a and b; -> Option A

4. Quick Check:

   Concurrent assignment = combinational logic [OK]

Hint: Combinational logic comes from simple concurrent assignments [OK]

Common Mistakes:

• Choosing clocked processes for combinational logic
• Confusing constants or signals with logic inference
• Ignoring the absence of clock edges

3. Given the following VHDL code, what hardware resource is inferred?

process(clk, a, b)
begin
  if rising_edge(clk) then
    q <= a or b;
  end if;
end process;

medium

A. Combinational logic only

B. Register (flip-flop) with combinational logic inside

C. Constant value

D. Latch

Solution

1. Step 1: Analyze the process sensitivity and clock usage

   The process is sensitive to clk, a, and b, but the assignment happens only on rising_edge(clk), indicating a clocked process.

2. Step 2: Determine inferred hardware

   Because the assignment is inside a clock edge condition, a register (flip-flop) is inferred. The expression 'a or b' is combinational logic feeding the register input.

3. Final Answer:

   Register (flip-flop) with combinational logic inside -> Option B

4. Quick Check:

   Clock edge + logic = register with combinational input [OK]

Hint: Clock edge inside process means register inferred [OK]

Common Mistakes:

• Ignoring the clock edge and thinking it's pure combinational
• Confusing latch with register
• Assuming constants are inferred

4. Identify the error in this VHDL code that prevents correct resource inference:

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

medium

A. Signal q is not declared

B. Process sensitivity list is empty

C. Missing rising_edge(clk) condition for clocked process

D. Constant d is used instead of signal

Solution

1. Step 1: Check clock condition usage

   The process uses 'if clk = '1'' instead of 'if rising_edge(clk)', which is the standard way to infer registers.

2. Step 2: Understand impact on resource inference

   Without rising_edge(clk), the compiler may infer a latch or incorrect hardware instead of a register.

3. Final Answer:

   Missing rising_edge(clk) condition for clocked process -> Option C

4. Quick Check:

   Use rising_edge(clk) for registers [OK]

Hint: Always use rising_edge(clk) for registers [OK]

Common Mistakes:

• Using level-sensitive clock check instead of edge
• Ignoring sensitivity list correctness
• Assuming signal declarations cause inference errors

5. You want to infer a 4-bit register with asynchronous reset in VHDL. Which code snippet correctly follows resource inference rules?

hard

A. process(reset) begin if reset = '1' then q <= (others => '0'); end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); else q <= d; end if; end if; end process;

C. q <= d when reset = '0' else (others => '0');

D. process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify asynchronous reset structure

   An asynchronous reset requires the reset signal in the sensitivity list and a separate if condition before the clock edge check.

2. Step 2: Check each option for correct inference

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; has reset and clk in sensitivity list, checks reset first, then rising_edge(clk), correctly inferring a register with async reset.

3. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; -> Option D

4. Quick Check:

   Async reset in sensitivity + if reset first = correct [OK]

Hint: Async reset must be checked before clock edge in process [OK]

Common Mistakes:

• Placing reset check inside clock edge condition (sync reset)
• Missing reset in sensitivity list for async reset
• Using conditional assignments outside process for registers