Resource inference rules in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of inferred resource for signal assignment

What is the inferred hardware resource for the following VHDL code snippet?

signal a, b, c : std_logic;
begin
  c <= a and b;

VHDL

signal a, b, c : std_logic;
begin
  c <= a and b;

A A multiplexer is inferred.

B A 2-input OR gate is inferred.

C A flip-flop is inferred.

D A 2-input AND gate is inferred.

💡 Hint

Think about what hardware corresponds to the 'and' operation on signals.

The 'and' operator on std_logic signals infers a 2-input AND gate in hardware.

❓ Predict Output

intermediate

Resource inferred by a process with clock and reset

What hardware resource is inferred by this VHDL process?

process(clk, rst)
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

VHDL

process(clk, rst)
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

A A D-type flip-flop with asynchronous reset is inferred.

B A D-type flip-flop with synchronous reset is inferred.

C A latch is inferred.

D A combinational logic block is inferred.

💡 Hint

Check if reset is inside the clock edge condition or outside.

Because reset is in the sensitivity list and checked before the rising_edge(clk), it infers an asynchronous reset flip-flop.

🔧 Debug

advanced

Identify the error causing latch inference

Which option shows the code that will cause a latch to be inferred due to incomplete assignments inside a process?

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
  end if;
end process;

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
  end if;
end process;

A No latch is inferred because q is assigned inside the clock edge.

B A syntax error occurs because 'enable' is not declared.

C The code as is causes latch inference because q is not assigned when enable /= '1'.

D A combinational logic block is inferred.

💡 Hint

Think about what happens to q when enable is '0'.

Since q is not assigned when enable is '0', the synthesis tool infers a latch to hold the previous value.

🧠 Conceptual

advanced

Resource inference for case statement with full coverage

Given a VHDL process with a case statement that covers all possible values of a 2-bit signal, what resource is inferred?

process(sel, a, b, c, d)
begin
  case sel is
    when "00" => y <= a;
    when "01" => y <= b;
    when "10" => y <= c;
    when others => y <= d;
  end case;
end process;

VHDL

process(sel, a, b, c, d)
begin
  case sel is
    when "00" => y <= a;
    when "01" => y <= b;
    when "10" => y <= c;
    when others => y <= d;
  end case;
end process;

A A 4-to-1 multiplexer is inferred.

B A 2-input AND gate is inferred.

C A flip-flop is inferred.

D A decoder is inferred.

💡 Hint

Think about what hardware selects one input based on a selector signal.

The case statement with full coverage and combinational sensitivity infers a multiplexer selecting one input based on sel.

❓ Predict Output

expert

Output of resource inferred by nested if-else in clocked process

What hardware resource is inferred by this VHDL code?

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    else
      q <= q;
    end if;
  end if;
end process;

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    else
      q <= q;
    end if;
  end if;
end process;

A A latch is inferred due to incomplete assignment.

B A D flip-flop with enable signal is inferred.

C A combinational logic block is inferred.

D A flip-flop with asynchronous reset is inferred.

💡 Hint

Assigning q <= q inside clocked process simulates enable behavior.

Assigning q <= q in the else branch prevents latch inference and models a flip-flop with enable control.

Practice

1. Which VHDL construct typically causes the compiler to infer a register (flip-flop)?

easy

A. A clocked process with a rising_edge(clock) condition

B. A simple concurrent signal assignment

C. A combinational process without clock sensitivity

D. A constant declaration

Solution

1. Step 1: Understand what infers registers

   Registers (flip-flops) are inferred when signals are assigned inside a process triggered by a clock edge, such as rising_edge(clock).

2. Step 2: Identify the correct construct

   A clocked process with rising_edge(clock) matches this condition, so it infers registers.

3. Final Answer:

   A clocked process with a rising_edge(clock) condition -> Option A

4. Quick Check:

   Clocked process = register inference [OK]

Hint: Registers come from clocked processes with edge checks [OK]

Common Mistakes:

• Confusing combinational assignments with registers
• Thinking constants infer registers
• Ignoring the clock edge condition

2. Which of the following VHDL code snippets correctly infers combinational logic?

easy

A. q <= a and b;

B. signal r : std_logic_vector(3 downto 0);

C. constant c : integer := 5;

D. process(clk) begin if rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify combinational logic inference

   Combinational logic is inferred from concurrent signal assignments or processes without clock edges.

2. Step 2: Check each option

   q <= a and b; is a concurrent assignment using logical AND, which infers combinational logic.

3. Final Answer:

   q <= a and b; -> Option A

4. Quick Check:

   Concurrent assignment = combinational logic [OK]

Hint: Combinational logic comes from simple concurrent assignments [OK]

Common Mistakes:

• Choosing clocked processes for combinational logic
• Confusing constants or signals with logic inference
• Ignoring the absence of clock edges

3. Given the following VHDL code, what hardware resource is inferred?

process(clk, a, b)
begin
  if rising_edge(clk) then
    q <= a or b;
  end if;
end process;

medium

A. Combinational logic only

B. Register (flip-flop) with combinational logic inside

C. Constant value

D. Latch

Solution

1. Step 1: Analyze the process sensitivity and clock usage

   The process is sensitive to clk, a, and b, but the assignment happens only on rising_edge(clk), indicating a clocked process.

2. Step 2: Determine inferred hardware

   Because the assignment is inside a clock edge condition, a register (flip-flop) is inferred. The expression 'a or b' is combinational logic feeding the register input.

3. Final Answer:

   Register (flip-flop) with combinational logic inside -> Option B

4. Quick Check:

   Clock edge + logic = register with combinational input [OK]

Hint: Clock edge inside process means register inferred [OK]

Common Mistakes:

• Ignoring the clock edge and thinking it's pure combinational
• Confusing latch with register
• Assuming constants are inferred

4. Identify the error in this VHDL code that prevents correct resource inference:

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

medium

A. Signal q is not declared

B. Process sensitivity list is empty

C. Missing rising_edge(clk) condition for clocked process

D. Constant d is used instead of signal

Solution

1. Step 1: Check clock condition usage

   The process uses 'if clk = '1'' instead of 'if rising_edge(clk)', which is the standard way to infer registers.

2. Step 2: Understand impact on resource inference

   Without rising_edge(clk), the compiler may infer a latch or incorrect hardware instead of a register.

3. Final Answer:

   Missing rising_edge(clk) condition for clocked process -> Option C

4. Quick Check:

   Use rising_edge(clk) for registers [OK]

Hint: Always use rising_edge(clk) for registers [OK]

Common Mistakes:

• Using level-sensitive clock check instead of edge
• Ignoring sensitivity list correctness
• Assuming signal declarations cause inference errors

5. You want to infer a 4-bit register with asynchronous reset in VHDL. Which code snippet correctly follows resource inference rules?

hard

A. process(reset) begin if reset = '1' then q <= (others => '0'); end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); else q <= d; end if; end if; end process;

C. q <= d when reset = '0' else (others => '0');

D. process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify asynchronous reset structure

   An asynchronous reset requires the reset signal in the sensitivity list and a separate if condition before the clock edge check.

2. Step 2: Check each option for correct inference

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; has reset and clk in sensitivity list, checks reset first, then rising_edge(clk), correctly inferring a register with async reset.

3. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; -> Option D

4. Quick Check:

   Async reset in sensitivity + if reset first = correct [OK]

Hint: Async reset must be checked before clock edge in process [OK]

Common Mistakes:

• Placing reset check inside clock edge condition (sync reset)
• Missing reset in sensitivity list for async reset
• Using conditional assignments outside process for registers