Reset strategy selection in VHDL - Step-by-Step Execution

Concept Flow - Reset strategy selection

Start

↓

Check Reset Type

↓

Synchronous Reset?

Yes→Reset on Clock Edge

↓

Asynchronous Reset?

Yes→Reset Immediately

↓

No Reset or Other Handling

↓

Continue Normal Operation

The reset strategy checks if the reset is synchronous or asynchronous and applies the reset accordingly before continuing normal operation.

Execution Sample

VHDL

process(clk, rst)
begin
  if rst = '1' then
    q <= (others => '0'); -- async reset
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

This VHDL process uses an asynchronous reset to clear 'q' immediately when 'rst' is high, otherwise it updates 'q' on the clock's rising edge.

Execution Table

Step	Signal Values	Condition Checked	Branch Taken	Output q
1	rst='0', clk rising edge	rst='1'?	No	q updated to d
2	rst='1', clk any	rst='1'?	Yes	q reset to 0
3	rst='0', clk no edge	rst='1'?	No	q unchanged
4	rst='0', clk rising edge	rst='1'?	No	q updated to d
5	rst='1', clk rising edge	rst='1'?	Yes	q reset to 0

💡 Process waits for events on clk or rst; resets when rst='1', otherwise updates q on clk rising edge.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
rst	'0'	'0'	'1'	'0'	'0'	'1'
clk	no edge	rising edge	any	no edge	rising edge	rising edge
q	unknown	d	0	0	d	0

Key Moments - 2 Insights

Why does 'q' reset immediately when 'rst' is '1' even if there is no clock edge?

Because the reset is asynchronous, the condition 'rst = 1' is checked independently of the clock, so 'q' resets immediately as shown in rows 2 and 5 of the execution_table.

What happens to 'q' when 'rst' is '0' but there is no rising clock edge?

The process does not update 'q' because the clock edge condition is not met, so 'q' remains unchanged as shown in row 3 of the execution_table.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'q' after step 2 when rst='1'?

A unchanged

B d

C '0'

D unknown

💡 Hint

Check row 2 in execution_table where rst='1' causes q to reset to 0.

At which step does the process update 'q' on a rising clock edge with rst='0'?

A Step 1

B Step 5

C Step 3

D Step 2

💡 Hint

Look for rows where rst='0' and clk has a rising edge that updates q.

If the reset was synchronous instead of asynchronous, how would the output 'q' behave when rst='1' but no clock edge occurs?

A q resets immediately

B q remains unchanged

C q updates to d

D q becomes unknown

💡 Hint

Synchronous reset only acts on clock edges; check variable_tracker and execution_table logic.

Concept Snapshot

Reset Strategy Selection in VHDL:
- Asynchronous reset triggers immediately when reset signal is active.
- Synchronous reset triggers only on clock edge when reset is active.
- Use 'if rst = '1' then' before clock edge check for async reset.
- Use 'if rising_edge(clk) then if rst = '1' then' for sync reset.
- Choose reset type based on design needs and timing requirements.

Full Transcript

This visual execution trace shows how a VHDL process handles reset signals. The process listens to both clock and reset signals. When the reset signal is '1', the output 'q' resets immediately regardless of the clock edge, demonstrating an asynchronous reset. If reset is '0', the output 'q' updates only on the rising edge of the clock. The execution table tracks signal values and output changes step-by-step. Key moments clarify why asynchronous reset acts immediately and why no update happens without a clock edge. The quiz tests understanding of reset behavior and timing. The snapshot summarizes how to select and implement reset strategies in VHDL.

Practice

1. Which statement best describes an asynchronous reset in VHDL?

easy

A. It requires a special reset clock signal to activate.

B. It resets the circuit immediately, independent of the clock.

C. It resets the circuit only on the rising edge of the clock.

D. It resets the circuit only after a delay of several clock cycles.

Solution

1. Step 1: Understand asynchronous reset behavior

   An asynchronous reset acts immediately when activated, without waiting for the clock signal.

2. Step 2: Compare with synchronous reset

   Synchronous reset waits for the clock edge, unlike asynchronous reset which is independent of the clock.

3. Final Answer:

   It resets the circuit immediately, independent of the clock. -> Option B

4. Quick Check:

   Asynchronous reset = immediate reset [OK]

Hint: Asynchronous reset ignores clock, acts immediately [OK]

Common Mistakes:

• Confusing asynchronous with synchronous reset
• Thinking reset waits for clock edge
• Assuming reset needs a special clock

2. Which VHDL code snippet correctly implements a synchronous reset for a flip-flop?

easy

A. process(reset) begin if reset = '1' then q <= '0'; end if; end process;

B. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

C. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

D. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify synchronous reset structure

   Synchronous reset checks reset inside the clock edge condition, so reset is applied only on clock rising edge.

2. Step 2: Analyze each option

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; checks reset inside rising_edge(clk), which is correct for synchronous reset. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; uses asynchronous reset sensitivity. process(reset) begin if reset = '1' then q <= '0'; end if; end process; is asynchronous and incomplete. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; checks reset outside clock edge, incorrect for synchronous.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option C

4. Quick Check:

   Synchronous reset inside clock edge = process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; [OK]

Hint: Synchronous reset inside rising_edge(clk) block [OK]

Common Mistakes:

• Putting reset check outside clock edge
• Using reset in sensitivity list for synchronous reset
• Confusing asynchronous and synchronous reset syntax

3. Given this VHDL process with asynchronous reset:

process(clk, rst) begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

What is the value of q after reset rst goes high, regardless of clock?

medium

A. Previous value of q retained

B. Value of d at next clock edge

C. Undefined until next clock edge

D. '0' immediately

Solution

1. Step 1: Understand asynchronous reset effect

   When rst is '1', the process sets q to '0' immediately, ignoring clock.

2. Step 2: Confirm behavior regardless of clock

   Because rst is in sensitivity list and checked first, q resets immediately when rst = '1'.

3. Final Answer:

   '0' immediately -> Option D

4. Quick Check:

   Asynchronous reset sets q to '0' immediately [OK]

Hint: Asynchronous reset sets output immediately, ignoring clock [OK]

Common Mistakes:

• Thinking reset waits for clock edge
• Assuming q keeps old value during reset
• Confusing asynchronous with synchronous reset

4. Identify the error in this VHDL code implementing synchronous reset:

process(clk, reset) begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. Reset should be in sensitivity list only if asynchronous

B. Reset check must be outside rising_edge(clk)

C. Missing else clause for reset condition

D. Process should not have clk in sensitivity list

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset requires only clock in sensitivity list; including reset causes unnecessary triggers.

2. Step 2: Confirm reset check inside clock edge is correct

   Reset is checked inside rising_edge(clk), which is correct for synchronous reset.

3. Final Answer:

   Reset should be in sensitivity list only if asynchronous -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Moving reset check outside clock edge for synchronous reset
• Confusing sensitivity list rules

5. You want a reset that ensures your circuit starts immediately after power-on but avoids glitches during clock transitions. Which reset strategy should you choose?

hard

A. Asynchronous reset with glitch filter circuit

B. Synchronous reset only

C. Asynchronous reset without any filtering

D. No reset, rely on power-on default states

Solution

1. Step 1: Understand immediate reset need

   Immediate reset after power-on requires asynchronous reset to act without waiting for clock.

2. Step 2: Avoid glitches during clock transitions

   Asynchronous resets can cause glitches; adding a glitch filter or synchronizer avoids this problem.

3. Final Answer:

   Asynchronous reset with glitch filter circuit -> Option A

4. Quick Check:

   Immediate reset + glitch avoidance = asynchronous with filter [OK]

Hint: Use async reset plus filter to avoid glitches [OK]

Common Mistakes:

• Choosing synchronous reset only (delays reset)
• Using async reset without glitch protection
• Assuming power-on defaults are reliable