Reset strategy selection in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of asynchronous reset process

What is the output signal q after the following process runs with rst = '1' and then rst goes to '0'?

VHDL

process(clk, rst)
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= not q;
  end if;
end process;

A q remains '0' forever once rst is '1'

B q is reset to '0' immediately when rst = '1', then toggles on each rising clock edge after rst = '0'

C q toggles on each rising clock edge regardless of rst value

D q toggles only when rst = '1' and clock rises

💡 Hint

Remember asynchronous reset triggers immediately when rst = '1'.

The asynchronous reset (sensitivity to rst) forces q to '0' immediately when rst = '1'. When rst returns to '0', q toggles on rising clock edges.

❓ Predict Output

intermediate

Synchronous reset behavior output

Given this process with synchronous reset, what is the value of q after the first rising clock edge when rst = '1'?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      q <= '0';
    else
      q <= not q;
    end if;
  end if;
end process;

A q toggles immediately when rst = '1' regardless of clock

B q toggles only when rst = '0'

C q is reset to '0' at the first rising clock edge when rst = '1'

D q remains unchanged when rst = '1'

💡 Hint

Synchronous reset only affects q on clock edges.

Since reset is synchronous, q is set to '0' only at the rising clock edge when rst = '1'.

🔧 Debug

advanced

Identify error in mixed reset sensitivity list

What error will occur with this process sensitivity list and reset logic?

VHDL

process(clk)
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= not q;
  end if;
end process;

A No error; process works as intended

B Syntax error due to missing rst in sensitivity list

C q resets asynchronously but may cause simulation mismatch

D q will never reset asynchronously because rst is not in sensitivity list

💡 Hint

Check sensitivity list for asynchronous signals.

Since rst is not in the sensitivity list, the process does not trigger immediately on rst changes, so asynchronous reset won't work properly.

❓ Predict Output

advanced

Output of reset synchronization circuit

What is the output sync_rst after applying an asynchronous reset arst = '1' for one clock cycle in this synchronization circuit?

VHDL

process(clk, arst)
begin
  if arst = '1' then
    sync_rst_1 <= '1';
    sync_rst <= '1';
  elsif rising_edge(clk) then
    sync_rst_1 <= '0';
    sync_rst <= sync_rst_1;
  end if;
end process;

A sync_rst stays '1' for two clock cycles after arst = '1' is released

B sync_rst resets immediately when arst = '1'

C sync_rst never goes to '1'

D sync_rst stays '1' indefinitely after arst = '1'

💡 Hint

Synchronization delays asynchronous reset by two flip-flops.

sync_rst_1 and sync_rst form a two-stage synchronizer delaying the reset release by two clock cycles.

🧠 Conceptual

expert

Choosing reset strategy for FPGA design

Which reset strategy is best for a high-speed FPGA design to minimize timing issues and metastability?

A Use synchronous reset only, avoiding asynchronous resets

B Use asynchronous reset with synchronization flip-flops on release

C Use asynchronous reset without synchronization

D Use both asynchronous and synchronous resets simultaneously

💡 Hint

Consider timing closure and metastability risks.

Synchronous resets avoid asynchronous release issues and simplify timing, making them preferred in high-speed FPGA designs.

Practice

1. Which statement best describes an asynchronous reset in VHDL?

easy

A. It requires a special reset clock signal to activate.

B. It resets the circuit immediately, independent of the clock.

C. It resets the circuit only on the rising edge of the clock.

D. It resets the circuit only after a delay of several clock cycles.

Solution

1. Step 1: Understand asynchronous reset behavior

   An asynchronous reset acts immediately when activated, without waiting for the clock signal.

2. Step 2: Compare with synchronous reset

   Synchronous reset waits for the clock edge, unlike asynchronous reset which is independent of the clock.

3. Final Answer:

   It resets the circuit immediately, independent of the clock. -> Option B

4. Quick Check:

   Asynchronous reset = immediate reset [OK]

Hint: Asynchronous reset ignores clock, acts immediately [OK]

Common Mistakes:

• Confusing asynchronous with synchronous reset
• Thinking reset waits for clock edge
• Assuming reset needs a special clock

2. Which VHDL code snippet correctly implements a synchronous reset for a flip-flop?

easy

A. process(reset) begin if reset = '1' then q <= '0'; end if; end process;

B. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

C. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

D. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify synchronous reset structure

   Synchronous reset checks reset inside the clock edge condition, so reset is applied only on clock rising edge.

2. Step 2: Analyze each option

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; checks reset inside rising_edge(clk), which is correct for synchronous reset. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; uses asynchronous reset sensitivity. process(reset) begin if reset = '1' then q <= '0'; end if; end process; is asynchronous and incomplete. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; checks reset outside clock edge, incorrect for synchronous.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option C

4. Quick Check:

   Synchronous reset inside clock edge = process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; [OK]

Hint: Synchronous reset inside rising_edge(clk) block [OK]

Common Mistakes:

• Putting reset check outside clock edge
• Using reset in sensitivity list for synchronous reset
• Confusing asynchronous and synchronous reset syntax

3. Given this VHDL process with asynchronous reset:

process(clk, rst) begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

What is the value of q after reset rst goes high, regardless of clock?

medium

A. Previous value of q retained

B. Value of d at next clock edge

C. Undefined until next clock edge

D. '0' immediately

Solution

1. Step 1: Understand asynchronous reset effect

   When rst is '1', the process sets q to '0' immediately, ignoring clock.

2. Step 2: Confirm behavior regardless of clock

   Because rst is in sensitivity list and checked first, q resets immediately when rst = '1'.

3. Final Answer:

   '0' immediately -> Option D

4. Quick Check:

   Asynchronous reset sets q to '0' immediately [OK]

Hint: Asynchronous reset sets output immediately, ignoring clock [OK]

Common Mistakes:

• Thinking reset waits for clock edge
• Assuming q keeps old value during reset
• Confusing asynchronous with synchronous reset

4. Identify the error in this VHDL code implementing synchronous reset:

process(clk, reset) begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. Reset should be in sensitivity list only if asynchronous

B. Reset check must be outside rising_edge(clk)

C. Missing else clause for reset condition

D. Process should not have clk in sensitivity list

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset requires only clock in sensitivity list; including reset causes unnecessary triggers.

2. Step 2: Confirm reset check inside clock edge is correct

   Reset is checked inside rising_edge(clk), which is correct for synchronous reset.

3. Final Answer:

   Reset should be in sensitivity list only if asynchronous -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Moving reset check outside clock edge for synchronous reset
• Confusing sensitivity list rules

5. You want a reset that ensures your circuit starts immediately after power-on but avoids glitches during clock transitions. Which reset strategy should you choose?

hard

A. Asynchronous reset with glitch filter circuit

B. Synchronous reset only

C. Asynchronous reset without any filtering

D. No reset, rely on power-on default states

Solution

1. Step 1: Understand immediate reset need

   Immediate reset after power-on requires asynchronous reset to act without waiting for clock.

2. Step 2: Avoid glitches during clock transitions

   Asynchronous resets can cause glitches; adding a glitch filter or synchronizer avoids this problem.

3. Final Answer:

   Asynchronous reset with glitch filter circuit -> Option A

4. Quick Check:

   Immediate reset + glitch avoidance = asynchronous with filter [OK]

Hint: Use async reset plus filter to avoid glitches [OK]

Common Mistakes:

• Choosing synchronous reset only (delays reset)
• Using async reset without glitch protection
• Assuming power-on defaults are reliable