Reset strategy selection in VHDL - Mini Project: Build & Apply

Reset Strategy Selection in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that requires a reset signal. Different reset strategies can be used, such as synchronous reset or asynchronous reset. Choosing the right reset strategy is important for reliable circuit behavior.

🎯 Goal: Build a VHDL module that implements a flip-flop with a selectable reset strategy. You will create a signal to select between synchronous and asynchronous reset, write the process with the chosen reset style, and then output the result.

📋 What You'll Learn

Create a signal called reset_strategy that selects between synchronous (0) and asynchronous (1) reset.

Write a process that uses reset_strategy to apply the correct reset behavior to a flip-flop output q.

Use a clock signal clk and an active-high reset signal rst.

Print the final value of q after applying reset and clock events.

💡 Why This Matters

🌍 Real World

Reset strategies are critical in digital circuit design to ensure reliable startup and operation of hardware components.

💼 Career

Understanding reset mechanisms is essential for hardware engineers and FPGA designers working on synchronous digital systems.

1

Create signals for clock, reset, and output

Create signals called clk, rst, and q of type std_logic. Initialize clk and rst to '0'.

VHDL

signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal q : std_logic;
-- Your code here

Hint

Use signal keyword and initialize clk and rst to '0'.

2

Add a signal to select reset strategy

Add a signal called reset_strategy of type std_logic initialized to '0' for synchronous reset.

VHDL

signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal q : std_logic;
signal reset_strategy : std_logic := '0';
-- Your code here

Hint

Use signal reset_strategy : std_logic := '0'; to select synchronous reset by default.

3

Write a process implementing reset strategy selection

Write a process sensitive to clk and rst that updates q. Use if reset_strategy = '1' for asynchronous reset: if rst = '1' then q <= '0'. Else, on rising edge of clk, if rst = '1' then q <= '0' else q <= '1'.

VHDL

signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal q : std_logic;
signal reset_strategy : std_logic := '0';

process(clk, rst)
begin
    -- Your code here
end process;

Hint

Use if reset_strategy = '1' to choose asynchronous reset logic, otherwise synchronous reset inside rising edge clock check.

4

Print the output signal q

Write a statement to print the value of q using report in VHDL.

VHDL

signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal q : std_logic;
signal reset_strategy : std_logic := '0';

process(clk, rst)
begin
    if reset_strategy = '1' then  -- asynchronous reset
        if rst = '1' then
            q <= '0';
        elsif rising_edge(clk) then
            q <= '1';
        end if;
    else  -- synchronous reset
        if rising_edge(clk) then
            if rst = '1' then
                q <= '0';
            else
                q <= '1';
            end if;
        end if;
    end if;
end process;

report "Value of q: " & std_logic'image(q);
-- Your code here

Hint

Use report "Value of q: " & std_logic'image(q); to print the signal value.

Practice

1. Which statement best describes an asynchronous reset in VHDL?

easy

A. It requires a special reset clock signal to activate.

B. It resets the circuit immediately, independent of the clock.

C. It resets the circuit only on the rising edge of the clock.

D. It resets the circuit only after a delay of several clock cycles.

Solution

1. Step 1: Understand asynchronous reset behavior

   An asynchronous reset acts immediately when activated, without waiting for the clock signal.

2. Step 2: Compare with synchronous reset

   Synchronous reset waits for the clock edge, unlike asynchronous reset which is independent of the clock.

3. Final Answer:

   It resets the circuit immediately, independent of the clock. -> Option B

4. Quick Check:

   Asynchronous reset = immediate reset [OK]

Hint: Asynchronous reset ignores clock, acts immediately [OK]

Common Mistakes:

• Confusing asynchronous with synchronous reset
• Thinking reset waits for clock edge
• Assuming reset needs a special clock

2. Which VHDL code snippet correctly implements a synchronous reset for a flip-flop?

easy

A. process(reset) begin if reset = '1' then q <= '0'; end if; end process;

B. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

C. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

D. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify synchronous reset structure

   Synchronous reset checks reset inside the clock edge condition, so reset is applied only on clock rising edge.

2. Step 2: Analyze each option

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; checks reset inside rising_edge(clk), which is correct for synchronous reset. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; uses asynchronous reset sensitivity. process(reset) begin if reset = '1' then q <= '0'; end if; end process; is asynchronous and incomplete. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; checks reset outside clock edge, incorrect for synchronous.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option C

4. Quick Check:

   Synchronous reset inside clock edge = process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; [OK]

Hint: Synchronous reset inside rising_edge(clk) block [OK]

Common Mistakes:

• Putting reset check outside clock edge
• Using reset in sensitivity list for synchronous reset
• Confusing asynchronous and synchronous reset syntax

3. Given this VHDL process with asynchronous reset:

process(clk, rst) begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

What is the value of q after reset rst goes high, regardless of clock?

medium

A. Previous value of q retained

B. Value of d at next clock edge

C. Undefined until next clock edge

D. '0' immediately

Solution

1. Step 1: Understand asynchronous reset effect

   When rst is '1', the process sets q to '0' immediately, ignoring clock.

2. Step 2: Confirm behavior regardless of clock

   Because rst is in sensitivity list and checked first, q resets immediately when rst = '1'.

3. Final Answer:

   '0' immediately -> Option D

4. Quick Check:

   Asynchronous reset sets q to '0' immediately [OK]

Hint: Asynchronous reset sets output immediately, ignoring clock [OK]

Common Mistakes:

• Thinking reset waits for clock edge
• Assuming q keeps old value during reset
• Confusing asynchronous with synchronous reset

4. Identify the error in this VHDL code implementing synchronous reset:

process(clk, reset) begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. Reset should be in sensitivity list only if asynchronous

B. Reset check must be outside rising_edge(clk)

C. Missing else clause for reset condition

D. Process should not have clk in sensitivity list

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset requires only clock in sensitivity list; including reset causes unnecessary triggers.

2. Step 2: Confirm reset check inside clock edge is correct

   Reset is checked inside rising_edge(clk), which is correct for synchronous reset.

3. Final Answer:

   Reset should be in sensitivity list only if asynchronous -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Moving reset check outside clock edge for synchronous reset
• Confusing sensitivity list rules

5. You want a reset that ensures your circuit starts immediately after power-on but avoids glitches during clock transitions. Which reset strategy should you choose?

hard

A. Asynchronous reset with glitch filter circuit

B. Synchronous reset only

C. Asynchronous reset without any filtering

D. No reset, rely on power-on default states

Solution

1. Step 1: Understand immediate reset need

   Immediate reset after power-on requires asynchronous reset to act without waiting for clock.

2. Step 2: Avoid glitches during clock transitions

   Asynchronous resets can cause glitches; adding a glitch filter or synchronizer avoids this problem.

3. Final Answer:

   Asynchronous reset with glitch filter circuit -> Option A

4. Quick Check:

   Immediate reset + glitch avoidance = asynchronous with filter [OK]

Hint: Use async reset plus filter to avoid glitches [OK]

Common Mistakes:

• Choosing synchronous reset only (delays reset)
• Using async reset without glitch protection
• Assuming power-on defaults are reliable