Procedure with signal parameters in VHDL - Step-by-Step Execution

Concept Flow - Procedure with signal parameters

Call Procedure

↓

Pass signal as parameter

↓

Procedure executes using signal

↓

Signal updated inside procedure

↓

Return to calling process

↓

Signal reflects changes

This flow shows how a signal is passed to a procedure, updated inside it, and the changes reflect back in the calling process.

Execution Sample

VHDL

procedure increment_signal(signal s : inout std_logic_vector(3 downto 0)) is
begin
  s <= std_logic_vector(unsigned(s) + 1);
end procedure;

This procedure takes a signal vector and increments its value by 1.

Execution Table

Step	Signal s Before	Action	Signal s After	Notes
1	"0000"	Call procedure increment_signal with s	"0000"	Initial signal value
2	"0000"	Increment s by 1 inside procedure	"0001"	Signal updated inside procedure
3	"0001"	Return from procedure	"0001"	Signal reflects updated value

💡 Procedure completes and signal s is updated to '0001'

Variable Tracker

Signal	Start	After Step 2	Final
s	"0000"	"0001"	"0001"

Key Moments - 2 Insights

Why does the signal s update outside the procedure after the procedure call?

Because the signal s is passed as an inout parameter, changes inside the procedure affect the original signal, as shown in execution_table step 3.

Can we pass variables instead of signals to this procedure?

No, this procedure expects a signal parameter (inout mode). Variables cannot be passed as signals, so the procedure requires a signal to work correctly.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of signal s after step 2?

A "0000"

B "0001"

C "0010"

D "1111"

💡 Hint

Check the 'Signal s After' column in step 2 of the execution_table.

At which step does the signal s get updated inside the procedure?

A Step 2

B Step 3

C Step 1

D Signal never updates

💡 Hint

Look at the 'Action' column describing the increment inside the procedure.

If the procedure parameter was declared as 'variable' instead of 'signal', what would happen?

A The original signal s would update as before

B The procedure would not compile

C Only a local copy would update, original signal s stays the same

D Signal s would reset to zero

💡 Hint

Consider how variables differ from signals in VHDL parameter passing.

Concept Snapshot

procedure proc_name(signal param : inout type) is
begin
  -- modify param
end procedure;

- Signal parameters allow procedures to read and update signals.
- Changes inside procedure affect the original signal.
- Use 'inout' mode for read/write signals.

Full Transcript

This visual trace shows how a VHDL procedure with a signal parameter works. The procedure increment_signal takes a signal s as an inout parameter. Initially, s is '0000'. When the procedure is called, it increments s by 1 inside the procedure. After the procedure finishes, the signal s outside the procedure reflects the updated value '0001'. This happens because signals passed as inout parameters allow the procedure to modify the original signal. Variables behave differently and would not update the original signal. This example helps beginners see step-by-step how signal parameters work in VHDL procedures.

Practice

1. What is the main purpose of using a procedure with signal parameters in VHDL?

easy

A. To allow the procedure to directly read and modify signals inside a process

B. To declare variables local to the procedure

C. To create constants that cannot be changed

D. To define new data types

Solution

1. Step 1: Understand signal parameters in procedures

   Signal parameters allow procedures to access and modify signals directly, unlike variables which are local copies.

2. Step 2: Identify the purpose of procedures with signal parameters

   They help reuse code that changes signals inside processes, making designs cleaner and modular.

3. Final Answer:

   To allow the procedure to directly read and modify signals inside a process -> Option A

4. Quick Check:

   Signal parameters modify signals directly [OK]

Hint: Signal parameters let procedures change signals directly [OK]

Common Mistakes:

• Confusing signal parameters with variables
• Thinking procedures cannot modify signals
• Assuming procedures only read signals

2. Which of the following is the correct way to declare a procedure with an out signal parameter in VHDL?

easy

A. procedure update_signal(constant s : out std_logic) is

B. procedure update_signal(variable s : out std_logic) is

C. procedure update_signal(signal s : out std_logic) is

D. procedure update_signal(signal s : in std_logic) is

Solution

1. Step 1: Recall signal parameter syntax

   Signal parameters must be declared with the keyword signal and direction in, out, or inout.

2. Step 2: Identify correct declaration

   procedure update_signal(signal s : out std_logic) is correctly declares a procedure with an out signal parameter. The others use incorrect keywords like constant or variable, or wrong direction in.

3. Final Answer:

   procedure update_signal(signal s : out std_logic) is -> Option C

4. Quick Check:

   Signal parameters use 'signal' keyword and direction [OK]

Hint: Use 'signal' keyword with direction for signal parameters [OK]

Common Mistakes:

• Using 'variable' instead of 'signal' for signal parameters
• Omitting the direction (in/out/inout)
• Using 'constant' keyword incorrectly

3. Consider the following VHDL code snippet inside a process:

signal a : std_logic := '0';

procedure toggle_signal(signal s : inout std_logic) is
begin
  if s = '0' then
    s <= '1';
  else
    s <= '0';
  end if;
end procedure;

begin
  toggle_signal(a);
end process;

What will be the value of signal a after the process runs once?

medium

A. Signal assignment error

B. '0'

C. Undefined

D. '1'

Solution

1. Step 1: Analyze initial value and procedure logic

   Signal a starts at '0'. The procedure toggles it: if '0', assign '1'; else assign '0'.

2. Step 2: Apply procedure to signal a

   Since a is '0', the procedure sets it to '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   Toggle '0' to '1' [OK]

Hint: Toggle flips '0' to '1' and vice versa [OK]

Common Mistakes:

• Confusing signal assignment timing (<= is scheduled)
• Assuming value stays '0' after toggle
• Thinking procedure cannot modify signals

4. Identify the error in the following VHDL procedure declaration:

procedure set_high(signal s : in std_logic) is
begin
  s <= '1';
end procedure;

medium

A. Missing variable declaration

B. Signal parameter cannot be declared as in if it is assigned inside

C. Procedure must return a value

D. Signal parameters cannot be used in procedures

Solution

1. Step 1: Check signal parameter direction

   The parameter s is declared as in, meaning it cannot be assigned a new value inside the procedure.

2. Step 2: Identify assignment conflict

   The procedure tries to assign s <= '1';, which is illegal for in signals. It should be out or inout.

3. Final Answer:

   Signal parameter cannot be declared as in if it is assigned inside -> Option B

4. Quick Check:

   Only out or inout signals can be assigned [OK]

Hint: Assign only to out or inout signal parameters [OK]

Common Mistakes:

• Assigning to an 'in' signal parameter
• Thinking procedures must return values
• Confusing variables and signals

5. You want to create a procedure that increments a 4-bit signal counter by 1 each time it is called. Which of the following procedure declarations and bodies correctly achieve this?

hard

A. procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

B. procedure increment_counter(signal cnt : in std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

C. procedure increment_counter(variable cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt := std_logic_vector(unsigned(cnt) + 1);
end procedure;

D. procedure increment_counter(signal cnt : out std_logic_vector(3 downto 0)) is
begin
cnt <= cnt + 1;
end procedure;

Solution

1. Step 1: Check parameter declaration

   The signal parameter must be declared as inout to read and write the signal inside the procedure.

2. Step 2: Verify increment logic and syntax

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; correctly converts cnt to unsigned, adds 1, then converts back to std_logic_vector and assigns with <=.

3. Step 3: Identify errors in other options

   The in version cannot assign to the signal, the variable version is not for signals, the out version lacks type conversion and reads uninitialized value.

4. Final Answer:

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; -> Option A

5. Quick Check:

   Use inout signal and proper type conversion [OK]

Hint: Use inout signal and convert types for arithmetic [OK]

Common Mistakes:

• Using 'in' direction when assigning signals
• Confusing variables and signals in procedures
• Skipping type conversion for arithmetic