Procedure with signal parameters in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL procedure call?

Given the following VHDL code snippet, what will be the value of signal_out after the procedure call?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity test_proc is
  port(
    signal_in : in std_logic_vector(3 downto 0);
    signal_out : out std_logic_vector(3 downto 0)
  );
end test_proc;

architecture behavior of test_proc is
  procedure invert_signal(signal s_in : in std_logic_vector(3 downto 0); signal s_out : out std_logic_vector(3 downto 0)) is
  begin
    for i in s_in'range loop
      s_out(i) <= not s_in(i);
    end loop;
  end procedure;
begin
  process(signal_in)
  begin
    invert_signal(signal_in, signal_out);
  end process;
end behavior;

A "signal_out = \"0101\" when signal_in = \"0101\""

B "signal_out = \"1111\" when signal_in = \"0101\""

C "signal_out = \"1010\" when signal_in = \"0101\""

D "signal_out = \"0000\" when signal_in = \"0101\""

💡 Hint

Remember that not inverts each bit in std_logic_vector.

The procedure invert_signal inverts each bit of signal_in and assigns it to signal_out. For input 0101, the output is 1010.

🧠 Conceptual

intermediate

Which statement about signal parameters in VHDL procedures is correct?

Consider signal parameters in VHDL procedures. Which of the following statements is true?

A Signal parameters can be used to pass signals by reference, allowing the procedure to modify the signal's value.

B Signal parameters in procedures behave exactly like variables and cannot drive signals outside the procedure.

C Signal parameters cannot be used in procedures; only variables can be passed.

D Signal parameters must always be declared as <code>in</code> mode and cannot be <code>out</code> or <code>inout</code>.

💡 Hint

Think about how signals are passed and updated in VHDL procedures.

Signal parameters in VHDL procedures allow passing signals by reference, so the procedure can modify the signal's value directly.

🔧 Debug

advanced

Identify the error in this VHDL procedure with signal parameters

What error will this VHDL code produce?

VHDL

procedure update_signal(signal s : in std_logic_vector(3 downto 0)) is
begin
  s <= "1111";
end procedure;

A Compilation error: Cannot assign to an <code>in</code> mode signal parameter.

B Runtime error: Signal assignment causes conflict.

C No error: The procedure works correctly and updates the signal.

D Compilation error: Missing <code>out</code> mode for signal parameter.

💡 Hint

Check the mode of the signal parameter and whether it can be assigned inside the procedure.

Signal parameters declared as in mode cannot be assigned new values inside the procedure, causing a compilation error.

📝 Syntax

advanced

Which option correctly declares a procedure with signal parameters in VHDL?

Choose the correct syntax for a procedure that takes one in and one out signal parameter of type std_logic_vector(7 downto 0).

A

procedure proc(signal a : in std_logic_vector(7 downto 0); b : out std_logic_vector(7 downto 0)) is
begin
  null;
end procedure;

B

procedure proc(a : in std_logic_vector(7 downto 0); b : out std_logic_vector(7 downto 0)) is
begin
  null;
end procedure;

C

procedure proc(signal a : std_logic_vector(7 downto 0); signal b : std_logic_vector(7 downto 0)) is
begin
  null;
end procedure;

D

procedure proc(signal a : in std_logic_vector(7 downto 0); signal b : out std_logic_vector(7 downto 0)) is
begin
  null;
end procedure;

💡 Hint

Remember to specify signal keyword and modes for signal parameters.

Signal parameters must be declared with the signal keyword and their mode (in, out, or inout).

🚀 Application

expert

How many signal assignments occur after this procedure call?

Consider the following VHDL code snippet:

signal a, b : std_logic_vector(1 downto 0);

procedure swap_signals(signal x : inout std_logic_vector(1 downto 0); signal y : inout std_logic_vector(1 downto 0)) is
  variable temp : std_logic_vector(1 downto 0);
begin
  temp := x;
  x <= y;
  y <= temp;
end procedure;

-- In a process:
swap_signals(a, b);

How many signal assignments are scheduled after the procedure call?

A 0

B 2

C 1

D 3

💡 Hint

Count the number of signal assignments inside the procedure.

The procedure assigns to x and y signals once each, so two signal assignments are scheduled.

Practice

1. What is the main purpose of using a procedure with signal parameters in VHDL?

easy

A. To allow the procedure to directly read and modify signals inside a process

B. To declare variables local to the procedure

C. To create constants that cannot be changed

D. To define new data types

Solution

1. Step 1: Understand signal parameters in procedures

   Signal parameters allow procedures to access and modify signals directly, unlike variables which are local copies.

2. Step 2: Identify the purpose of procedures with signal parameters

   They help reuse code that changes signals inside processes, making designs cleaner and modular.

3. Final Answer:

   To allow the procedure to directly read and modify signals inside a process -> Option A

4. Quick Check:

   Signal parameters modify signals directly [OK]

Hint: Signal parameters let procedures change signals directly [OK]

Common Mistakes:

• Confusing signal parameters with variables
• Thinking procedures cannot modify signals
• Assuming procedures only read signals

2. Which of the following is the correct way to declare a procedure with an out signal parameter in VHDL?

easy

A. procedure update_signal(constant s : out std_logic) is

B. procedure update_signal(variable s : out std_logic) is

C. procedure update_signal(signal s : out std_logic) is

D. procedure update_signal(signal s : in std_logic) is

Solution

1. Step 1: Recall signal parameter syntax

   Signal parameters must be declared with the keyword signal and direction in, out, or inout.

2. Step 2: Identify correct declaration

   procedure update_signal(signal s : out std_logic) is correctly declares a procedure with an out signal parameter. The others use incorrect keywords like constant or variable, or wrong direction in.

3. Final Answer:

   procedure update_signal(signal s : out std_logic) is -> Option C

4. Quick Check:

   Signal parameters use 'signal' keyword and direction [OK]

Hint: Use 'signal' keyword with direction for signal parameters [OK]

Common Mistakes:

• Using 'variable' instead of 'signal' for signal parameters
• Omitting the direction (in/out/inout)
• Using 'constant' keyword incorrectly

3. Consider the following VHDL code snippet inside a process:

signal a : std_logic := '0';

procedure toggle_signal(signal s : inout std_logic) is
begin
  if s = '0' then
    s <= '1';
  else
    s <= '0';
  end if;
end procedure;

begin
  toggle_signal(a);
end process;

What will be the value of signal a after the process runs once?

medium

A. Signal assignment error

B. '0'

C. Undefined

D. '1'

Solution

1. Step 1: Analyze initial value and procedure logic

   Signal a starts at '0'. The procedure toggles it: if '0', assign '1'; else assign '0'.

2. Step 2: Apply procedure to signal a

   Since a is '0', the procedure sets it to '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   Toggle '0' to '1' [OK]

Hint: Toggle flips '0' to '1' and vice versa [OK]

Common Mistakes:

• Confusing signal assignment timing (<= is scheduled)
• Assuming value stays '0' after toggle
• Thinking procedure cannot modify signals

4. Identify the error in the following VHDL procedure declaration:

procedure set_high(signal s : in std_logic) is
begin
  s <= '1';
end procedure;

medium

A. Missing variable declaration

B. Signal parameter cannot be declared as in if it is assigned inside

C. Procedure must return a value

D. Signal parameters cannot be used in procedures

Solution

1. Step 1: Check signal parameter direction

   The parameter s is declared as in, meaning it cannot be assigned a new value inside the procedure.

2. Step 2: Identify assignment conflict

   The procedure tries to assign s <= '1';, which is illegal for in signals. It should be out or inout.

3. Final Answer:

   Signal parameter cannot be declared as in if it is assigned inside -> Option B

4. Quick Check:

   Only out or inout signals can be assigned [OK]

Hint: Assign only to out or inout signal parameters [OK]

Common Mistakes:

• Assigning to an 'in' signal parameter
• Thinking procedures must return values
• Confusing variables and signals

5. You want to create a procedure that increments a 4-bit signal counter by 1 each time it is called. Which of the following procedure declarations and bodies correctly achieve this?

hard

A. procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

B. procedure increment_counter(signal cnt : in std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

C. procedure increment_counter(variable cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt := std_logic_vector(unsigned(cnt) + 1);
end procedure;

D. procedure increment_counter(signal cnt : out std_logic_vector(3 downto 0)) is
begin
cnt <= cnt + 1;
end procedure;

Solution

1. Step 1: Check parameter declaration

   The signal parameter must be declared as inout to read and write the signal inside the procedure.

2. Step 2: Verify increment logic and syntax

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; correctly converts cnt to unsigned, adds 1, then converts back to std_logic_vector and assigns with <=.

3. Step 3: Identify errors in other options

   The in version cannot assign to the signal, the variable version is not for signals, the out version lacks type conversion and reads uninitialized value.

4. Final Answer:

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; -> Option A

5. Quick Check:

   Use inout signal and proper type conversion [OK]

Hint: Use inout signal and convert types for arithmetic [OK]

Common Mistakes:

• Using 'in' direction when assigning signals
• Confusing variables and signals in procedures
• Skipping type conversion for arithmetic