Procedure with signal parameters in VHDL - Mini Project: Build & Apply

Procedure with signal parameters in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that needs to update a signal value using a procedure. Procedures with signal parameters allow you to change signals inside the procedure and see the effect outside.

🎯 Goal: Build a VHDL design with a procedure that takes a signal parameter and updates it. Then call this procedure to change a signal value and observe the output.

📋 What You'll Learn

Create a signal called counter of type integer.

Write a procedure called increment_counter that takes a signal parameter sig of type integer and increments it by 1.

Call the procedure increment_counter to update the counter signal.

Print the value of counter after calling the procedure.

💡 Why This Matters

🌍 Real World

Procedures with signal parameters are used in VHDL to modularize code that changes signals, such as counters, flags, or control signals in digital circuits.

💼 Career

Understanding how to write and use procedures with signal parameters is important for FPGA and ASIC design engineers who write clean and reusable VHDL code.

1

Create the signal counter

Declare a signal called counter of type integer initialized to 0 inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity CounterEntity is
end CounterEntity;

architecture Behavioral of CounterEntity is
    -- Declare signal counter here
    -- Your code here
begin

end Behavioral;

Hint

Signals are declared inside the architecture but before the begin keyword.

2

Write the procedure increment_counter

Inside the architecture, write a procedure called increment_counter that takes a signal parameter sig of type integer and increments it by 1.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity CounterEntity is
end CounterEntity;

architecture Behavioral of CounterEntity is
    signal counter : integer := 0;
    -- Write procedure increment_counter here
    -- Your code here
begin

end Behavioral;

Hint

Use signal sig : inout integer to allow the procedure to modify the signal.

3

Call the procedure to update counter

Inside the architecture body (after begin), call the procedure increment_counter passing the signal counter to increment its value.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity CounterEntity is
end CounterEntity;

architecture Behavioral of CounterEntity is
    signal counter : integer := 0;

    procedure increment_counter(signal sig : inout integer) is
    begin
        sig <= sig + 1;
    end procedure;
begin
    -- Call increment_counter with counter
    -- Your code here
end Behavioral;

Hint

Call the procedure by passing the signal name inside parentheses.

4

Print the value of counter

Add a process that waits for 0 ns and then prints the value of counter using report statement.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity CounterEntity is
end CounterEntity;

architecture Behavioral of CounterEntity is
    signal counter : integer := 0;

    procedure increment_counter(signal sig : inout integer) is
    begin
        sig <= sig + 1;
    end procedure;
begin
    increment_counter(counter);

    -- Add a process to print counter value
    -- Your code here
end Behavioral;

Hint

The report statement prints messages during simulation. Use integer'image(counter) to convert the integer to string.

Practice

1. What is the main purpose of using a procedure with signal parameters in VHDL?

easy

A. To allow the procedure to directly read and modify signals inside a process

B. To declare variables local to the procedure

C. To create constants that cannot be changed

D. To define new data types

Solution

1. Step 1: Understand signal parameters in procedures

   Signal parameters allow procedures to access and modify signals directly, unlike variables which are local copies.

2. Step 2: Identify the purpose of procedures with signal parameters

   They help reuse code that changes signals inside processes, making designs cleaner and modular.

3. Final Answer:

   To allow the procedure to directly read and modify signals inside a process -> Option A

4. Quick Check:

   Signal parameters modify signals directly [OK]

Hint: Signal parameters let procedures change signals directly [OK]

Common Mistakes:

• Confusing signal parameters with variables
• Thinking procedures cannot modify signals
• Assuming procedures only read signals

2. Which of the following is the correct way to declare a procedure with an out signal parameter in VHDL?

easy

A. procedure update_signal(constant s : out std_logic) is

B. procedure update_signal(variable s : out std_logic) is

C. procedure update_signal(signal s : out std_logic) is

D. procedure update_signal(signal s : in std_logic) is

Solution

1. Step 1: Recall signal parameter syntax

   Signal parameters must be declared with the keyword signal and direction in, out, or inout.

2. Step 2: Identify correct declaration

   procedure update_signal(signal s : out std_logic) is correctly declares a procedure with an out signal parameter. The others use incorrect keywords like constant or variable, or wrong direction in.

3. Final Answer:

   procedure update_signal(signal s : out std_logic) is -> Option C

4. Quick Check:

   Signal parameters use 'signal' keyword and direction [OK]

Hint: Use 'signal' keyword with direction for signal parameters [OK]

Common Mistakes:

• Using 'variable' instead of 'signal' for signal parameters
• Omitting the direction (in/out/inout)
• Using 'constant' keyword incorrectly

3. Consider the following VHDL code snippet inside a process:

signal a : std_logic := '0';

procedure toggle_signal(signal s : inout std_logic) is
begin
  if s = '0' then
    s <= '1';
  else
    s <= '0';
  end if;
end procedure;

begin
  toggle_signal(a);
end process;

What will be the value of signal a after the process runs once?

medium

A. Signal assignment error

B. '0'

C. Undefined

D. '1'

Solution

1. Step 1: Analyze initial value and procedure logic

   Signal a starts at '0'. The procedure toggles it: if '0', assign '1'; else assign '0'.

2. Step 2: Apply procedure to signal a

   Since a is '0', the procedure sets it to '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   Toggle '0' to '1' [OK]

Hint: Toggle flips '0' to '1' and vice versa [OK]

Common Mistakes:

• Confusing signal assignment timing (<= is scheduled)
• Assuming value stays '0' after toggle
• Thinking procedure cannot modify signals

4. Identify the error in the following VHDL procedure declaration:

procedure set_high(signal s : in std_logic) is
begin
  s <= '1';
end procedure;

medium

A. Missing variable declaration

B. Signal parameter cannot be declared as in if it is assigned inside

C. Procedure must return a value

D. Signal parameters cannot be used in procedures

Solution

1. Step 1: Check signal parameter direction

   The parameter s is declared as in, meaning it cannot be assigned a new value inside the procedure.

2. Step 2: Identify assignment conflict

   The procedure tries to assign s <= '1';, which is illegal for in signals. It should be out or inout.

3. Final Answer:

   Signal parameter cannot be declared as in if it is assigned inside -> Option B

4. Quick Check:

   Only out or inout signals can be assigned [OK]

Hint: Assign only to out or inout signal parameters [OK]

Common Mistakes:

• Assigning to an 'in' signal parameter
• Thinking procedures must return values
• Confusing variables and signals

5. You want to create a procedure that increments a 4-bit signal counter by 1 each time it is called. Which of the following procedure declarations and bodies correctly achieve this?

hard

A. procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

B. procedure increment_counter(signal cnt : in std_logic_vector(3 downto 0)) is
begin
cnt <= std_logic_vector(unsigned(cnt) + 1);
end procedure;

C. procedure increment_counter(variable cnt : inout std_logic_vector(3 downto 0)) is
begin
cnt := std_logic_vector(unsigned(cnt) + 1);
end procedure;

D. procedure increment_counter(signal cnt : out std_logic_vector(3 downto 0)) is
begin
cnt <= cnt + 1;
end procedure;

Solution

1. Step 1: Check parameter declaration

   The signal parameter must be declared as inout to read and write the signal inside the procedure.

2. Step 2: Verify increment logic and syntax

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; correctly converts cnt to unsigned, adds 1, then converts back to std_logic_vector and assigns with <=.

3. Step 3: Identify errors in other options

   The in version cannot assign to the signal, the variable version is not for signals, the out version lacks type conversion and reads uninitialized value.

4. Final Answer:

   procedure increment_counter(signal cnt : inout std_logic_vector(3 downto 0)) is begin cnt <= std_logic_vector(unsigned(cnt) + 1); end procedure; -> Option A

5. Quick Check:

   Use inout signal and proper type conversion [OK]

Hint: Use inout signal and convert types for arithmetic [OK]

Common Mistakes:

• Using 'in' direction when assigning signals
• Confusing variables and signals in procedures
• Skipping type conversion for arithmetic