Generic parameters for configurable modules in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a generic parameter named WIDTH with a default value of 8.

VHDL

entity my_module is
  generic (
    WIDTH : integer := [1]
  );
  port (
    input : in std_logic_vector(WIDTH-1 downto 0);
    output : out std_logic_vector(WIDTH-1 downto 0)
  );
end my_module;

Drag options to blanks, or click blank then click option'

A16

B4

C8

D32

Attempts:

3 left

💡 Hint

Common Mistakes

Using a value other than an integer for WIDTH.

Forgetting to assign a default value.

The generic WIDTH is set to 8 by default, which defines the bit width of the input and output ports.

2fill in blank

medium

Complete the code to use the generic WIDTH to define the size of the signal 'data'.

VHDL

architecture Behavioral of my_module is
  signal data : std_logic_vector([1]-1 downto 0);
begin
  -- logic here
end Behavioral;

Drag options to blanks, or click blank then click option'

AWIDTH

B8

C16

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Using a fixed number instead of the generic parameter.

Using an undefined identifier.

The signal 'data' uses the generic WIDTH to set its size dynamically.

3fill in blank

hard

Fix the error in the generic map to set WIDTH to 16 when instantiating the module.

VHDL

U1: entity work.my_module
  generic map (
    WIDTH => [1]
  )
  port map (
    input => input_signal,
    output => output_signal
  );

Drag options to blanks, or click blank then click option'

A8

BWIDTH

C32

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning the generic name instead of a value.

Using a value not declared or supported.

When instantiating, assign the generic WIDTH to 16 to override the default.

4fill in blank

hard

Fill both blanks to declare two generic parameters WIDTH and DEPTH with default values 8 and 16.

VHDL

entity memory is
  generic (
    WIDTH : integer := [1];
    DEPTH : integer := [2]
  );
  port (
    addr : in std_logic_vector(DEPTH-1 downto 0);
    data_in : in std_logic_vector(WIDTH-1 downto 0);
    data_out : out std_logic_vector(WIDTH-1 downto 0)
  );
end memory;

Drag options to blanks, or click blank then click option'

A8

B32

C16

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the values of WIDTH and DEPTH.

Using non-integer values.

WIDTH is set to 8 and DEPTH to 16 as default generic values.

5fill in blank

hard

Fill all three blanks to create a generic map that sets WIDTH to 16, DEPTH to 32, and MODE to 'FAST'.

VHDL

U_mem: entity work.memory
  generic map (
    WIDTH => [1],
    DEPTH => [2],
    MODE => [3]
  )
  port map (
    addr => addr_signal,
    data_in => data_in_signal,
    data_out => data_out_signal
  );

Drag options to blanks, or click blank then click option'

A8

B32

C'FAST'

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes for string literals.

Mixing up the values for WIDTH and DEPTH.

The generic map assigns WIDTH=16, DEPTH=32, and MODE='FAST' to configure the module.

Practice

1. What is the main purpose of generic parameters in a VHDL module?

easy

A. To declare variables local to a process

B. To define signals inside the architecture

C. To specify the clock frequency of the design

D. To customize module behavior without changing its internal code

Solution

1. Step 1: Understand the role of generics in VHDL

   Generics allow you to set parameters that can change module behavior without rewriting the module code.

2. Step 2: Compare with other options

   Signals and variables are different constructs; generics are not for clock frequency specifically.

3. Final Answer:

   To customize module behavior without changing its internal code -> Option D

4. Quick Check:

   Generics = customizable parameters [OK]

Hint: Generics customize modules without code changes [OK]

Common Mistakes:

• Confusing generics with signals or variables
• Thinking generics set clock frequency only
• Assuming generics are declared inside architecture

2. Which of the following is the correct syntax to declare a generic parameter named WIDTH of type integer with default value 8 in a VHDL entity?

easy

A. constant WIDTH : integer := 8;

B. generic WIDTH : integer = 8;

C. generic (WIDTH : integer := 8);

D. parameter WIDTH : integer := 8;

Solution

1. Step 1: Recall VHDL generic declaration syntax

   Generics are declared inside parentheses after the keyword generic with colon and default value using :=.

2. Step 2: Check each option

   generic (WIDTH : integer := 8); matches correct syntax: generic (WIDTH : integer := 8);. Others use incorrect keywords or syntax.

3. Final Answer:

   generic (WIDTH : integer := 8); -> Option C

4. Quick Check:

   Generic syntax uses parentheses and := [OK]

Hint: Generics use parentheses and := for defaults [OK]

Common Mistakes:

• Using '=' instead of ':=' for default values
• Confusing generics with constants or parameters
• Omitting parentheses around generic list

3. Given the following VHDL entity and architecture:

entity MyModule is
  generic (WIDTH : integer := 4);
  port (
    input : in std_logic_vector(WIDTH-1 downto 0);
    output : out std_logic_vector(WIDTH-1 downto 0)
  );
end MyModule;

architecture Behavioral of MyModule is
begin
  output <= input;
end Behavioral;

What will be the width of output if this module is instantiated with generic map (WIDTH => 8)?

medium

A. 8 bits

B. 4 bits

C. WIDTH bits (unknown)

D. 1 bit

Solution

1. Step 1: Understand generic override on instantiation

   The generic WIDTH default is 4, but overridden to 8 during instantiation.

2. Step 2: Calculate output width

   Output is std_logic_vector(WIDTH-1 downto 0), so with WIDTH=8, output is 8 bits wide.

3. Final Answer:

   8 bits -> Option A

4. Quick Check:

   Generic override sets WIDTH=8 [OK]

Hint: Generic override changes WIDTH to 8 bits [OK]

Common Mistakes:

• Ignoring generic override and using default 4
• Confusing WIDTH with signal length
• Assuming output is always 1 bit

4. Identify the error in this VHDL entity declaration:

entity ConfigurableCounter is
  generic WIDTH : integer := 8;
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end ConfigurableCounter;

medium

A. Missing parentheses around generic declaration

B. WIDTH should be declared as a signal, not generic

C. Port declaration syntax is incorrect

D. No error, declaration is correct

Solution

1. Step 1: Check generic declaration syntax

   Generics must be declared inside parentheses after the keyword generic.

2. Step 2: Analyze given code

   The code declares generic WIDTH : integer := 8; without parentheses, which is invalid syntax.

3. Final Answer:

   Missing parentheses around generic declaration -> Option A

4. Quick Check:

   Generics need parentheses [OK]

Hint: Always use parentheses for generics [OK]

Common Mistakes:

• Omitting parentheses in generic declaration
• Confusing generics with signals
• Assuming port syntax is wrong when it's correct

5. You want to create a VHDL module for a FIFO buffer where the depth and data width can be set using generics. Which of the following is the best way to declare these generics in the entity?

hard

A. generic DEPTH : integer := 16; WIDTH : integer := 8;

B. generic (DEPTH : integer := 16; WIDTH : integer := 8);

C. constant DEPTH : integer := 16; constant WIDTH : integer := 8;

D. signal DEPTH : integer := 16; signal WIDTH : integer := 8;

Solution

1. Step 1: Recall correct generic declaration for multiple parameters

   Multiple generics must be declared inside parentheses separated by semicolons.

2. Step 2: Evaluate each option

   generic (DEPTH : integer := 16; WIDTH : integer := 8); correctly declares both generics inside parentheses with default values. Options B, C, and D use incorrect keywords or syntax.

3. Final Answer:

   generic (DEPTH : integer := 16; WIDTH : integer := 8); -> Option B

4. Quick Check:

   Multiple generics use parentheses and semicolons [OK]

Hint: Use parentheses and semicolons for multiple generics [OK]

Common Mistakes:

• Declaring generics without parentheses
• Using constant or signal instead of generic
• Separating generics with commas instead of semicolons