Generic parameters for configurable modules in VHDL - Mini Project: Build & Apply

Generic parameters for configurable modules

📖 Scenario: You are designing a simple digital circuit module in VHDL that can be configured with different bit widths using generic parameters. This is common in hardware design to reuse the same module with different sizes.

🎯 Goal: Build a VHDL module called ConfigurableCounter that uses a generic parameter WIDTH to set the bit width of the counter. The counter will count from 0 up to the maximum value based on WIDTH.

📋 What You'll Learn

Create a VHDL entity called ConfigurableCounter with a generic parameter WIDTH of type integer.

Add a signal count inside the architecture with the bit width defined by WIDTH.

Implement a simple process that increments count on each rising clock edge and resets it to 0 when it reaches the maximum value.

Print or display the current value of count (simulate output) to verify the counter behavior.

💡 Why This Matters

🌍 Real World

Generic parameters allow hardware designers to create flexible modules that can be reused with different sizes or configurations without rewriting code.

💼 Career

Understanding generics in VHDL is essential for FPGA and ASIC design engineers to build scalable and maintainable hardware components.

1

Create the VHDL entity with generic parameter

Write the VHDL entity declaration for ConfigurableCounter with a generic parameter called WIDTH of type integer and a port clk of type std_logic.

VHDL

entity ConfigurableCounter is
    generic (
        WIDTH : integer
    );
    port (
        clk : in std_logic
    );
end ConfigurableCounter;

Hint

Remember to declare the generic parameter inside the generic block and the clock input inside the port block.

2

Add the signal count with width from generic

Inside the architecture of ConfigurableCounter, declare a signal called count of type std_logic_vector with a range from WIDTH-1 downto 0.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity ConfigurableCounter is
    generic (
        WIDTH : integer
    );
    port (
        clk : in std_logic
    );
end ConfigurableCounter;

architecture Behavioral of ConfigurableCounter is
    signal count : std_logic_vector(WIDTH-1 downto 0);
begin
    -- Your code here

Hint

Use std_logic_vector(WIDTH-1 downto 0) to declare the signal with the generic width.

3

Implement the counting process with reset at max value

Add a process triggered on the rising edge of clk that increments count by 1 each clock cycle. When count reaches the maximum value (all bits '1'), reset it to zero.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ConfigurableCounter is
    generic (
        WIDTH : integer
    );
    port (
        clk : in std_logic
    );
end ConfigurableCounter;

architecture Behavioral of ConfigurableCounter is
    signal count : std_logic_vector(WIDTH-1 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use unsigned conversion to add 1 to count. Reset when all bits are '1'.

4

Display the current value of count

Add a statement to print the current value of count as an unsigned integer inside the process after updating count. Use report statement with a message showing the count value.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ConfigurableCounter is
    generic (
        WIDTH : integer
    );
    port (
        clk : in std_logic
    );
end ConfigurableCounter;

architecture Behavioral of ConfigurableCounter is
    signal count : std_logic_vector(WIDTH-1 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if count = (others => '1') then
                count  '0');
            else
                count <= std_logic_vector(unsigned(count) + 1);
            end if;
            -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use report with string concatenation and integer'image to display the count.

Practice

1. What is the main purpose of generic parameters in a VHDL module?

easy

A. To declare variables local to a process

B. To define signals inside the architecture

C. To specify the clock frequency of the design

D. To customize module behavior without changing its internal code

Solution

1. Step 1: Understand the role of generics in VHDL

   Generics allow you to set parameters that can change module behavior without rewriting the module code.

2. Step 2: Compare with other options

   Signals and variables are different constructs; generics are not for clock frequency specifically.

3. Final Answer:

   To customize module behavior without changing its internal code -> Option D

4. Quick Check:

   Generics = customizable parameters [OK]

Hint: Generics customize modules without code changes [OK]

Common Mistakes:

• Confusing generics with signals or variables
• Thinking generics set clock frequency only
• Assuming generics are declared inside architecture

2. Which of the following is the correct syntax to declare a generic parameter named WIDTH of type integer with default value 8 in a VHDL entity?

easy

A. constant WIDTH : integer := 8;

B. generic WIDTH : integer = 8;

C. generic (WIDTH : integer := 8);

D. parameter WIDTH : integer := 8;

Solution

1. Step 1: Recall VHDL generic declaration syntax

   Generics are declared inside parentheses after the keyword generic with colon and default value using :=.

2. Step 2: Check each option

   generic (WIDTH : integer := 8); matches correct syntax: generic (WIDTH : integer := 8);. Others use incorrect keywords or syntax.

3. Final Answer:

   generic (WIDTH : integer := 8); -> Option C

4. Quick Check:

   Generic syntax uses parentheses and := [OK]

Hint: Generics use parentheses and := for defaults [OK]

Common Mistakes:

• Using '=' instead of ':=' for default values
• Confusing generics with constants or parameters
• Omitting parentheses around generic list

3. Given the following VHDL entity and architecture:

entity MyModule is
  generic (WIDTH : integer := 4);
  port (
    input : in std_logic_vector(WIDTH-1 downto 0);
    output : out std_logic_vector(WIDTH-1 downto 0)
  );
end MyModule;

architecture Behavioral of MyModule is
begin
  output <= input;
end Behavioral;

What will be the width of output if this module is instantiated with generic map (WIDTH => 8)?

medium

A. 8 bits

B. 4 bits

C. WIDTH bits (unknown)

D. 1 bit

Solution

1. Step 1: Understand generic override on instantiation

   The generic WIDTH default is 4, but overridden to 8 during instantiation.

2. Step 2: Calculate output width

   Output is std_logic_vector(WIDTH-1 downto 0), so with WIDTH=8, output is 8 bits wide.

3. Final Answer:

   8 bits -> Option A

4. Quick Check:

   Generic override sets WIDTH=8 [OK]

Hint: Generic override changes WIDTH to 8 bits [OK]

Common Mistakes:

• Ignoring generic override and using default 4
• Confusing WIDTH with signal length
• Assuming output is always 1 bit

4. Identify the error in this VHDL entity declaration:

entity ConfigurableCounter is
  generic WIDTH : integer := 8;
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end ConfigurableCounter;

medium

A. Missing parentheses around generic declaration

B. WIDTH should be declared as a signal, not generic

C. Port declaration syntax is incorrect

D. No error, declaration is correct

Solution

1. Step 1: Check generic declaration syntax

   Generics must be declared inside parentheses after the keyword generic.

2. Step 2: Analyze given code

   The code declares generic WIDTH : integer := 8; without parentheses, which is invalid syntax.

3. Final Answer:

   Missing parentheses around generic declaration -> Option A

4. Quick Check:

   Generics need parentheses [OK]

Hint: Always use parentheses for generics [OK]

Common Mistakes:

• Omitting parentheses in generic declaration
• Confusing generics with signals
• Assuming port syntax is wrong when it's correct

5. You want to create a VHDL module for a FIFO buffer where the depth and data width can be set using generics. Which of the following is the best way to declare these generics in the entity?

hard

A. generic DEPTH : integer := 16; WIDTH : integer := 8;

B. generic (DEPTH : integer := 16; WIDTH : integer := 8);

C. constant DEPTH : integer := 16; constant WIDTH : integer := 8;

D. signal DEPTH : integer := 16; signal WIDTH : integer := 8;

Solution

1. Step 1: Recall correct generic declaration for multiple parameters

   Multiple generics must be declared inside parentheses separated by semicolons.

2. Step 2: Evaluate each option

   generic (DEPTH : integer := 16; WIDTH : integer := 8); correctly declares both generics inside parentheses with default values. Options B, C, and D use incorrect keywords or syntax.

3. Final Answer:

   generic (DEPTH : integer := 16; WIDTH : integer := 8); -> Option B

4. Quick Check:

   Multiple generics use parentheses and semicolons [OK]

Hint: Use parentheses and semicolons for multiple generics [OK]

Common Mistakes:

• Declaring generics without parentheses
• Using constant or signal instead of generic
• Separating generics with commas instead of semicolons