Generic parameters for configurable modules in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a generic parameter in VHDL?

A generic parameter is a constant value that you can set when you instantiate a module. It lets you customize the module's behavior or size without changing its code.

beginner

How do you declare a generic parameter in a VHDL entity?

You declare generic parameters inside the entity using the generic keyword followed by the parameter name, type, and default value.

beginner

Why use generic parameters instead of hardcoding values in VHDL modules?

Generic parameters make modules reusable and flexible. You can change sizes or behaviors without rewriting the module, saving time and reducing errors.

intermediate

Example: How to instantiate a VHDL module with a generic parameter set to 8?

When instantiating, use the generic map clause to assign the value. For example:
U1: entity work.my_module generic map (WIDTH => 8) port map (...);

intermediate

Can generic parameters be changed during simulation or runtime?

No, generic parameters are constants set at compile or instantiation time. They cannot be changed during simulation or runtime.

Where do you declare generic parameters in a VHDL module?

A Inside the architecture body

B In the package file

C In the testbench only

D Inside the entity declaration

Generic parameters are declared inside the entity declaration using the generic keyword.

How do you assign a value to a generic parameter when instantiating a module?

A Using generic map clause

B Using port map clause

C By changing the entity code

D By setting a signal value

You assign generic parameters using the generic map clause during instantiation.

What happens if you do not specify a generic parameter value during instantiation?

A The default value declared in the entity is used

B The compiler throws an error

C The parameter is set to zero

D The module will not compile

If no value is given, the default value declared in the entity is used.

Can generic parameters be signals that change during simulation?

A Yes, they can change anytime

B No, they are constants set at compile time

C Only if declared as variables

D Only in testbenches

Generic parameters are constants and cannot change during simulation.

Which keyword is used to declare generic parameters in VHDL?

A constant

B parameter

C generic

D signal

The keyword generic is used to declare generic parameters.

Explain how generic parameters help make VHDL modules configurable and reusable.

Think about how you can change module behavior without rewriting it.

Describe the steps to declare and use a generic parameter in a VHDL module.

Start from the entity declaration to instantiation.

Practice

1. What is the main purpose of generic parameters in a VHDL module?

easy

A. To declare variables local to a process

B. To define signals inside the architecture

C. To specify the clock frequency of the design

D. To customize module behavior without changing its internal code

Solution

1. Step 1: Understand the role of generics in VHDL

   Generics allow you to set parameters that can change module behavior without rewriting the module code.

2. Step 2: Compare with other options

   Signals and variables are different constructs; generics are not for clock frequency specifically.

3. Final Answer:

   To customize module behavior without changing its internal code -> Option D

4. Quick Check:

   Generics = customizable parameters [OK]

Hint: Generics customize modules without code changes [OK]

Common Mistakes:

• Confusing generics with signals or variables
• Thinking generics set clock frequency only
• Assuming generics are declared inside architecture

2. Which of the following is the correct syntax to declare a generic parameter named WIDTH of type integer with default value 8 in a VHDL entity?

easy

A. constant WIDTH : integer := 8;

B. generic WIDTH : integer = 8;

C. generic (WIDTH : integer := 8);

D. parameter WIDTH : integer := 8;

Solution

1. Step 1: Recall VHDL generic declaration syntax

   Generics are declared inside parentheses after the keyword generic with colon and default value using :=.

2. Step 2: Check each option

   generic (WIDTH : integer := 8); matches correct syntax: generic (WIDTH : integer := 8);. Others use incorrect keywords or syntax.

3. Final Answer:

   generic (WIDTH : integer := 8); -> Option C

4. Quick Check:

   Generic syntax uses parentheses and := [OK]

Hint: Generics use parentheses and := for defaults [OK]

Common Mistakes:

• Using '=' instead of ':=' for default values
• Confusing generics with constants or parameters
• Omitting parentheses around generic list

3. Given the following VHDL entity and architecture:

entity MyModule is
  generic (WIDTH : integer := 4);
  port (
    input : in std_logic_vector(WIDTH-1 downto 0);
    output : out std_logic_vector(WIDTH-1 downto 0)
  );
end MyModule;

architecture Behavioral of MyModule is
begin
  output <= input;
end Behavioral;

What will be the width of output if this module is instantiated with generic map (WIDTH => 8)?

medium

A. 8 bits

B. 4 bits

C. WIDTH bits (unknown)

D. 1 bit

Solution

1. Step 1: Understand generic override on instantiation

   The generic WIDTH default is 4, but overridden to 8 during instantiation.

2. Step 2: Calculate output width

   Output is std_logic_vector(WIDTH-1 downto 0), so with WIDTH=8, output is 8 bits wide.

3. Final Answer:

   8 bits -> Option A

4. Quick Check:

   Generic override sets WIDTH=8 [OK]

Hint: Generic override changes WIDTH to 8 bits [OK]

Common Mistakes:

• Ignoring generic override and using default 4
• Confusing WIDTH with signal length
• Assuming output is always 1 bit

4. Identify the error in this VHDL entity declaration:

entity ConfigurableCounter is
  generic WIDTH : integer := 8;
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end ConfigurableCounter;

medium

A. Missing parentheses around generic declaration

B. WIDTH should be declared as a signal, not generic

C. Port declaration syntax is incorrect

D. No error, declaration is correct

Solution

1. Step 1: Check generic declaration syntax

   Generics must be declared inside parentheses after the keyword generic.

2. Step 2: Analyze given code

   The code declares generic WIDTH : integer := 8; without parentheses, which is invalid syntax.

3. Final Answer:

   Missing parentheses around generic declaration -> Option A

4. Quick Check:

   Generics need parentheses [OK]

Hint: Always use parentheses for generics [OK]

Common Mistakes:

• Omitting parentheses in generic declaration
• Confusing generics with signals
• Assuming port syntax is wrong when it's correct

5. You want to create a VHDL module for a FIFO buffer where the depth and data width can be set using generics. Which of the following is the best way to declare these generics in the entity?

hard

A. generic DEPTH : integer := 16; WIDTH : integer := 8;

B. generic (DEPTH : integer := 16; WIDTH : integer := 8);

C. constant DEPTH : integer := 16; constant WIDTH : integer := 8;

D. signal DEPTH : integer := 16; signal WIDTH : integer := 8;

Solution

1. Step 1: Recall correct generic declaration for multiple parameters

   Multiple generics must be declared inside parentheses separated by semicolons.

2. Step 2: Evaluate each option

   generic (DEPTH : integer := 16; WIDTH : integer := 8); correctly declares both generics inside parentheses with default values. Options B, C, and D use incorrect keywords or syntax.

3. Final Answer:

   generic (DEPTH : integer := 16; WIDTH : integer := 8); -> Option B

4. Quick Check:

   Multiple generics use parentheses and semicolons [OK]

Hint: Use parentheses and semicolons for multiple generics [OK]

Common Mistakes:

• Declaring generics without parentheses
• Using constant or signal instead of generic
• Separating generics with commas instead of semicolons