Edge detector design in VHDL - Step-by-Step Execution

Concept Flow - Edge detector design

Input Signal

↓

Store Previous State

↓

Compare Current and Previous

↓

Rising Edge Detected

↓

No Edge

↓

Output Edge Signal

The design stores the previous input value, compares it with the current input, and outputs a signal when a rising edge (0 to 1) is detected.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    edge_detected <= input_signal and not prev_signal;
    prev_signal <= input_signal;
  end if;
end process;

This VHDL process detects a rising edge on input_signal by comparing it with its previous value on each clock cycle.

Execution Table

Step	clk rising_edge?	input_signal	prev_signal (before)	edge_detected	prev_signal (after)
1	Yes	0	0	0 and not 0 = 0	0
2	Yes	1	0	1 and not 0 = 1 (rising edge)	1
3	Yes	1	1	1 and not 1 = 0	1
4	Yes	0	1	0 and not 1 = 0	0
5	Yes	1	0	1 and not 0 = 1 (rising edge)	1

💡 Process runs on every rising clock edge; no exit condition as it is continuous.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
input_signal	0	0	1	1	0	1
prev_signal	0	0	1	1	0	1
edge_detected	0	0	1	0	0	1

Key Moments - 2 Insights

Why does edge_detected become 1 only when input_signal changes from 0 to 1?

Because edge_detected is set to input_signal AND NOT prev_signal (row 2 and 5 in execution_table), it is 1 only when current input is 1 and previous input was 0, indicating a rising edge.

Why do we store prev_signal after computing edge_detected?

We use prev_signal from before updating to compare with current input. Updating prev_signal after computing edge_detected ensures the comparison uses the previous clock's input (see execution_table columns prev_signal before and after).

Visual Quiz - 3 Questions

Look at the execution_table at Step 3. What is the value of edge_detected?

A 1

B Undefined

C 0

D Same as input_signal

💡 Hint

Check the 'edge_detected' column at Step 3 in execution_table.

At which step does the first rising edge get detected?

A Step 2

B Step 1

C Step 4

D Step 3

💡 Hint

Look for where edge_detected changes from 0 to 1 in execution_table.

If input_signal stayed at 0 for all steps, what would edge_detected be?

A Always 1

B Always 0

C Alternates 0 and 1

D Depends on prev_signal

💡 Hint

Refer to the logic edge_detected = input_signal AND NOT prev_signal in execution_table.

Concept Snapshot

Edge detector in VHDL:
- Store previous input signal each clock cycle
- Compare current input and previous input
- Output 1 when input changes from 0 to 1 (rising edge)
- Use: edge_detected <= input_signal AND NOT prev_signal
- Update prev_signal after detection
- Runs on rising clock edge

Full Transcript

This VHDL edge detector design works by storing the previous input signal value on each rising clock edge. It compares the current input with the previous one. When the current input is 1 and the previous input was 0, it means a rising edge occurred, so the output edge_detected is set to 1. Otherwise, edge_detected is 0. The process repeats every clock cycle, continuously detecting rising edges. The key is to update the previous signal only after computing the edge detection to ensure correct comparison. The execution table shows step-by-step how input_signal, prev_signal, and edge_detected change over time.

Practice

1. What is the main purpose of an edge detector in VHDL?

easy

A. To generate a clock signal

B. To store a constant value permanently

C. To convert analog signals to digital

D. To detect changes in a signal from low to high or high to low

Solution

1. Step 1: Understand the role of edge detectors

   Edge detectors monitor signals to find when they change state, either rising or falling edges.

2. Step 2: Identify the correct function

   Detecting changes in signal levels is exactly what edge detectors do, unlike storing values or generating clocks.

3. Final Answer:

   To detect changes in a signal from low to high or high to low -> Option D

4. Quick Check:

   Edge detection = signal change detection [OK]

Hint: Edge detectors track signal changes, not constants or clocks [OK]

Common Mistakes:

• Confusing edge detection with clock generation
• Thinking edge detectors store constant values
• Assuming edge detectors convert signal types

2. Which VHDL code snippet correctly declares a signal to store the previous value for edge detection?

easy

A. signal prev_signal : integer range 0 to 1;

B. signal prev_signal : std_logic;

C. constant prev_signal : std_logic_vector(1 downto 0);

D. variable prev_signal : integer;

Solution

1. Step 1: Identify correct signal declaration for previous value

   For edge detection, we store the previous signal value as a signal of type std_logic.

2. Step 2: Compare options

   signal prev_signal : std_logic; declares a signal of type std_logic, suitable for storing previous signal state. Variables or constants are not appropriate here.

3. Final Answer:

   signal prev_signal : std_logic; -> Option B

4. Quick Check:

   Previous value storage = signal std_logic [OK]

Hint: Use 'signal' with std_logic for previous signal storage [OK]

Common Mistakes:

• Using variable instead of signal for previous value
• Declaring constant instead of signal
• Using incorrect data types like integer

3. Given the following VHDL process for a rising edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '1' and prev_signal = '0' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

What will be the value of edge_detected if signal_in changes from '0' to '1' at the clock edge?

medium

A. '0'

B. Undefined

C. '1'

D. Signal error

Solution

1. Step 1: Understand signal update timing in VHDL

   In VHDL, signal assignments inside a clocked process update after the process ends, so prev_signal still holds old value during evaluation.

2. Step 2: Evaluate condition at clock edge

   At the clock edge, prev_signal still equals '0' (old value), signal_in is '1'. prev_signal <= signal_in schedules update after process. Condition signal_in='1' and prev_signal='0' is true, so edge_detected <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Signal update delay enables edge detection with old prev_signal [OK]

Hint: prev_signal lags one cycle, allowing correct rising edge detection [OK]

Common Mistakes:

• Assuming prev_signal updates immediately within process
• Confusing signal and variable assignment timing
• Thinking edge_detected remains '0' due to update order

4. Identify the error in this VHDL code snippet for a falling edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '0' and prev_signal = '1' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

medium

A. No error; code is correct

B. prev_signal should be updated after edge_detected assignment

C. prev_signal must be a variable, not a signal

D. The condition should check for rising_edge(signal_in)

Solution

1. Step 1: Analyze signal update order

   Due to VHDL signal semantics, prev_signal retains its prior value ('1') during the condition check even though assigned first, allowing correct falling edge detection when signal_in='0'.

2. Step 2: Confirm code correctness

   This is the standard implementation for a synchronous falling edge detector; no error exists.

3. Final Answer:

   No error; code is correct -> Option A

4. Quick Check:

   Standard order works due to delta-delay updates [OK]

Hint: VHDL signal reads use pre-process values; code detects edge correctly [OK]

Common Mistakes:

• Misunderstanding that assignment order requires swapping
• Using rising_edge on signal_in instead of clk
• Declaring prev_signal as variable

5. You want to design an edge detector in VHDL that detects both rising and falling edges of a signal signal_in. Which approach correctly implements this?

hard

A. Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after

B. Use two separate processes for rising and falling edges with different clocks

C. Assign edge_detected <= '1' when signal_in = '1' else '0'; no previous value needed

D. Use a variable to store signal_in and assign edge_detected <= '1' when variable = '0'

Solution

1. Step 1: Understand dual edge detection logic

   Detecting both edges means detecting any change in signal_in compared to its previous value.

2. Step 2: Implement comparison and update order

   Comparing current and previous values with signal_in /= prev_signal detects any edge. Updating prev_signal after ensures correct timing.

3. Final Answer:

   Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after -> Option A

4. Quick Check:

   signal_in /= prev_signal detects any edge [OK]

Hint: Detect edges by comparing current and previous signal values [OK]

Common Mistakes:

• Using separate clocks for edge detection
• Ignoring previous signal value
• Assigning edge_detected based only on current signal