Edge detector design in VHDL - Mini Project: Build & Apply

Edge Detector Design

📖 Scenario: You are designing a simple digital circuit that detects a rising edge on a signal. This is useful in many electronics projects where you want to know when a signal changes from low to high.

🎯 Goal: Build a VHDL module that detects a rising edge on an input signal and outputs a pulse for one clock cycle when the rising edge occurs.

📋 What You'll Learn

Create a signal to hold the previous state of the input

Create a process triggered by the clock to update the previous state

Detect the rising edge by comparing current and previous input states

Output a pulse signal that is high for one clock cycle on a rising edge

💡 Why This Matters

🌍 Real World

Edge detectors are used in digital electronics to trigger actions exactly when a signal changes from low to high, such as button presses or sensor signals.

💼 Career

Understanding edge detection is important for FPGA and ASIC design engineers who create timing-sensitive digital circuits.

1

Create the input and output signals

Write the VHDL entity declaration named EdgeDetector with an input signal clk of type std_logic, an input signal signal_in of type std_logic, and an output signal rising_edge of type std_logic.

VHDL

-- Write the entity declaration for EdgeDetector with clk, signal_in, and rising_edge signals

Hint

Define an entity with the exact name EdgeDetector and the ports clk, signal_in, and rising_edge with the correct directions and types.

2

Add a signal to hold the previous input state

Inside the architecture named Behavior of EdgeDetector, declare a signal called prev_signal of type std_logic initialized to '0'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EdgeDetector is
    Port (
        clk : in std_logic;
        signal_in : in std_logic;
        rising_edge : out std_logic
    );
end EdgeDetector;

architecture Behavior of EdgeDetector is
    -- Declare prev_signal here
    -- Your code here
begin

end Behavior;

Hint

Declare a signal named prev_signal inside the architecture with initial value '0'.

3

Create a process to detect the rising edge

Inside the architecture Behavior, write a process triggered on the rising edge of clk. Inside the process, assign rising_edge to '1' if signal_in is '1' and prev_signal is '0', otherwise assign '0'. Then update prev_signal with the current signal_in value.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EdgeDetector is
    Port (
        clk : in std_logic;
        signal_in : in std_logic;
        rising_edge : out std_logic
    );
end EdgeDetector;

architecture Behavior of EdgeDetector is
    signal prev_signal : std_logic := '0';
begin

-- Write a process triggered by rising edge of clk
-- Inside process, detect rising edge and update prev_signal
-- Your code here

end Behavior;

Hint

Use a process sensitive to clk. Use if rising_edge(clk) then to detect clock edges. Inside, compare signal_in and prev_signal to set rising_edge. Update prev_signal at the end.

4

Test the edge detector output

Write a simple testbench process that applies the following signal_in values on consecutive clock cycles: '0', '0', '1', '1', '0', '1'. Print the value of rising_edge after each clock cycle using report statements.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Add a testbench process below to apply signal_in values and report rising_edge
-- Your code here

Hint

Create a testbench architecture with a clock signal toggling every 10 ns. Apply the input sequence to signal_in. Use report to print the rising_edge output after each clock rising edge.

Practice

1. What is the main purpose of an edge detector in VHDL?

easy

A. To generate a clock signal

B. To store a constant value permanently

C. To convert analog signals to digital

D. To detect changes in a signal from low to high or high to low

Solution

1. Step 1: Understand the role of edge detectors

   Edge detectors monitor signals to find when they change state, either rising or falling edges.

2. Step 2: Identify the correct function

   Detecting changes in signal levels is exactly what edge detectors do, unlike storing values or generating clocks.

3. Final Answer:

   To detect changes in a signal from low to high or high to low -> Option D

4. Quick Check:

   Edge detection = signal change detection [OK]

Hint: Edge detectors track signal changes, not constants or clocks [OK]

Common Mistakes:

• Confusing edge detection with clock generation
• Thinking edge detectors store constant values
• Assuming edge detectors convert signal types

2. Which VHDL code snippet correctly declares a signal to store the previous value for edge detection?

easy

A. signal prev_signal : integer range 0 to 1;

B. signal prev_signal : std_logic;

C. constant prev_signal : std_logic_vector(1 downto 0);

D. variable prev_signal : integer;

Solution

1. Step 1: Identify correct signal declaration for previous value

   For edge detection, we store the previous signal value as a signal of type std_logic.

2. Step 2: Compare options

   signal prev_signal : std_logic; declares a signal of type std_logic, suitable for storing previous signal state. Variables or constants are not appropriate here.

3. Final Answer:

   signal prev_signal : std_logic; -> Option B

4. Quick Check:

   Previous value storage = signal std_logic [OK]

Hint: Use 'signal' with std_logic for previous signal storage [OK]

Common Mistakes:

• Using variable instead of signal for previous value
• Declaring constant instead of signal
• Using incorrect data types like integer

3. Given the following VHDL process for a rising edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '1' and prev_signal = '0' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

What will be the value of edge_detected if signal_in changes from '0' to '1' at the clock edge?

medium

A. '0'

B. Undefined

C. '1'

D. Signal error

Solution

1. Step 1: Understand signal update timing in VHDL

   In VHDL, signal assignments inside a clocked process update after the process ends, so prev_signal still holds old value during evaluation.

2. Step 2: Evaluate condition at clock edge

   At the clock edge, prev_signal still equals '0' (old value), signal_in is '1'. prev_signal <= signal_in schedules update after process. Condition signal_in='1' and prev_signal='0' is true, so edge_detected <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Signal update delay enables edge detection with old prev_signal [OK]

Hint: prev_signal lags one cycle, allowing correct rising edge detection [OK]

Common Mistakes:

• Assuming prev_signal updates immediately within process
• Confusing signal and variable assignment timing
• Thinking edge_detected remains '0' due to update order

4. Identify the error in this VHDL code snippet for a falling edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '0' and prev_signal = '1' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

medium

A. No error; code is correct

B. prev_signal should be updated after edge_detected assignment

C. prev_signal must be a variable, not a signal

D. The condition should check for rising_edge(signal_in)

Solution

1. Step 1: Analyze signal update order

   Due to VHDL signal semantics, prev_signal retains its prior value ('1') during the condition check even though assigned first, allowing correct falling edge detection when signal_in='0'.

2. Step 2: Confirm code correctness

   This is the standard implementation for a synchronous falling edge detector; no error exists.

3. Final Answer:

   No error; code is correct -> Option A

4. Quick Check:

   Standard order works due to delta-delay updates [OK]

Hint: VHDL signal reads use pre-process values; code detects edge correctly [OK]

Common Mistakes:

• Misunderstanding that assignment order requires swapping
• Using rising_edge on signal_in instead of clk
• Declaring prev_signal as variable

5. You want to design an edge detector in VHDL that detects both rising and falling edges of a signal signal_in. Which approach correctly implements this?

hard

A. Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after

B. Use two separate processes for rising and falling edges with different clocks

C. Assign edge_detected <= '1' when signal_in = '1' else '0'; no previous value needed

D. Use a variable to store signal_in and assign edge_detected <= '1' when variable = '0'

Solution

1. Step 1: Understand dual edge detection logic

   Detecting both edges means detecting any change in signal_in compared to its previous value.

2. Step 2: Implement comparison and update order

   Comparing current and previous values with signal_in /= prev_signal detects any edge. Updating prev_signal after ensures correct timing.

3. Final Answer:

   Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after -> Option A

4. Quick Check:

   signal_in /= prev_signal detects any edge [OK]

Hint: Detect edges by comparing current and previous signal values [OK]

Common Mistakes:

• Using separate clocks for edge detection
• Ignoring previous signal value
• Assigning edge_detected based only on current signal