Edge detector design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a rising edge detector process

What is the output of the following VHDL process when the input signal sig_in changes from '0' to '1'?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    prev_sig <= sig_in;
    edge_detected <= '1' when (sig_in = '1' and prev_sig = '0') else '0';
  end if;
end process;

A edge_detected = '1' only on the clock cycle when sig_in changes from '0' to '1'

B edge_detected = '1' continuously as long as sig_in is '1'

C edge_detected = '0' always, no edge detected

D edge_detected toggles between '0' and '1' every clock cycle

💡 Hint

Think about how the previous signal value is stored and compared to detect a rising edge.

The process stores the previous value of sig_in in prev_sig. The output edge_detected is set to '1' only when the current sig_in is '1' and the previous was '0', which means a rising edge happened exactly at that clock cycle.

🧠 Conceptual

intermediate

Understanding edge detection signals

Which signal type is best suited to detect edges in VHDL designs?

A A signal that toggles randomly to simulate edges

B A signal that directly outputs the input value without any delay

C A constant signal that never changes

D A signal that stores the current and previous input values to compare changes

💡 Hint

Think about how you can tell if a signal just changed from one value to another.

To detect edges, you need to compare the current input value with its previous value. This requires storing the previous value in a signal and then comparing it to the current input.

🔧 Debug

advanced

Identify the error in this edge detector code

What error will occur when running this VHDL code for edge detection?

VHDL

process(clk)
begin
  if clk'event and clk = '1' then
    if sig_in = '1' and prev_sig = '0' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
    prev_sig <= sig_in;
  end if;
end process;

A prev_sig is used before being initialized, causing simulation mismatch

B Process will never trigger because clk'event is incorrect

C Syntax error due to missing semicolon

D No error; code works correctly

💡 Hint

Consider the initial value of prev_sig before the first clock cycle.

The signal prev_sig is used in the condition before it is assigned any initial value. This can cause simulation mismatches or unexpected behavior because prev_sig is undefined at the start.

📝 Syntax

advanced

Which code snippet correctly detects a falling edge?

Choose the VHDL code snippet that correctly detects a falling edge on sig_in signal.

A edge_detected <= '1' when (sig_in = '1' and prev_sig = '0') else '0';

B edge_detected <= '1' when (sig_in = '0' or prev_sig = '1') else '0';

C edge_detected <= '1' when (sig_in = '0' and prev_sig = '1') else '0';

D edge_detected <= '1' when (sig_in = '1' or prev_sig = '0') else '0';

💡 Hint

Falling edge means signal changes from '1' to '0'.

The falling edge is detected when the current signal is '0' and the previous signal was '1'. Option C correctly implements this condition.

🚀 Application

expert

Number of detected edges in a signal sequence

Given the input signal sequence over 8 clock cycles: sig_in = '0', '1', '1', '0', '1', '0', '0', '1', how many rising edges will the following edge detector detect?

process(clk)
begin
  if rising_edge(clk) then
    prev_sig <= sig_in;
    edge_detected <= '1' when (sig_in = '1' and prev_sig = '0') else '0';
  end if;
end process;

A 2

B 3

C 5

D 4

💡 Hint

Count how many times the signal changes from '0' to '1' in the sequence.

The rising edges occur when the signal changes from '0' to '1'. The transitions are at cycles: 0->1, 3->4, and 6->7 (indexing from 0). So total 3 rising edges.

Practice

1. What is the main purpose of an edge detector in VHDL?

easy

A. To generate a clock signal

B. To store a constant value permanently

C. To convert analog signals to digital

D. To detect changes in a signal from low to high or high to low

Solution

1. Step 1: Understand the role of edge detectors

   Edge detectors monitor signals to find when they change state, either rising or falling edges.

2. Step 2: Identify the correct function

   Detecting changes in signal levels is exactly what edge detectors do, unlike storing values or generating clocks.

3. Final Answer:

   To detect changes in a signal from low to high or high to low -> Option D

4. Quick Check:

   Edge detection = signal change detection [OK]

Hint: Edge detectors track signal changes, not constants or clocks [OK]

Common Mistakes:

• Confusing edge detection with clock generation
• Thinking edge detectors store constant values
• Assuming edge detectors convert signal types

2. Which VHDL code snippet correctly declares a signal to store the previous value for edge detection?

easy

A. signal prev_signal : integer range 0 to 1;

B. signal prev_signal : std_logic;

C. constant prev_signal : std_logic_vector(1 downto 0);

D. variable prev_signal : integer;

Solution

1. Step 1: Identify correct signal declaration for previous value

   For edge detection, we store the previous signal value as a signal of type std_logic.

2. Step 2: Compare options

   signal prev_signal : std_logic; declares a signal of type std_logic, suitable for storing previous signal state. Variables or constants are not appropriate here.

3. Final Answer:

   signal prev_signal : std_logic; -> Option B

4. Quick Check:

   Previous value storage = signal std_logic [OK]

Hint: Use 'signal' with std_logic for previous signal storage [OK]

Common Mistakes:

• Using variable instead of signal for previous value
• Declaring constant instead of signal
• Using incorrect data types like integer

3. Given the following VHDL process for a rising edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '1' and prev_signal = '0' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

What will be the value of edge_detected if signal_in changes from '0' to '1' at the clock edge?

medium

A. '0'

B. Undefined

C. '1'

D. Signal error

Solution

1. Step 1: Understand signal update timing in VHDL

   In VHDL, signal assignments inside a clocked process update after the process ends, so prev_signal still holds old value during evaluation.

2. Step 2: Evaluate condition at clock edge

   At the clock edge, prev_signal still equals '0' (old value), signal_in is '1'. prev_signal <= signal_in schedules update after process. Condition signal_in='1' and prev_signal='0' is true, so edge_detected <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Signal update delay enables edge detection with old prev_signal [OK]

Hint: prev_signal lags one cycle, allowing correct rising edge detection [OK]

Common Mistakes:

• Assuming prev_signal updates immediately within process
• Confusing signal and variable assignment timing
• Thinking edge_detected remains '0' due to update order

4. Identify the error in this VHDL code snippet for a falling edge detector:

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;
    if signal_in = '0' and prev_signal = '1' then
      edge_detected <= '1';
    else
      edge_detected <= '0';
    end if;
  end if;
end process;

medium

A. No error; code is correct

B. prev_signal should be updated after edge_detected assignment

C. prev_signal must be a variable, not a signal

D. The condition should check for rising_edge(signal_in)

Solution

1. Step 1: Analyze signal update order

   Due to VHDL signal semantics, prev_signal retains its prior value ('1') during the condition check even though assigned first, allowing correct falling edge detection when signal_in='0'.

2. Step 2: Confirm code correctness

   This is the standard implementation for a synchronous falling edge detector; no error exists.

3. Final Answer:

   No error; code is correct -> Option A

4. Quick Check:

   Standard order works due to delta-delay updates [OK]

Hint: VHDL signal reads use pre-process values; code detects edge correctly [OK]

Common Mistakes:

• Misunderstanding that assignment order requires swapping
• Using rising_edge on signal_in instead of clk
• Declaring prev_signal as variable

5. You want to design an edge detector in VHDL that detects both rising and falling edges of a signal signal_in. Which approach correctly implements this?

hard

A. Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after

B. Use two separate processes for rising and falling edges with different clocks

C. Assign edge_detected <= '1' when signal_in = '1' else '0'; no previous value needed

D. Use a variable to store signal_in and assign edge_detected <= '1' when variable = '0'

Solution

1. Step 1: Understand dual edge detection logic

   Detecting both edges means detecting any change in signal_in compared to its previous value.

2. Step 2: Implement comparison and update order

   Comparing current and previous values with signal_in /= prev_signal detects any edge. Updating prev_signal after ensures correct timing.

3. Final Answer:

   Compare current and previous values: edge_detected <= '1' when signal_in /= prev_signal else '0'; update prev_signal after -> Option A

4. Quick Check:

   signal_in /= prev_signal detects any edge [OK]

Hint: Detect edges by comparing current and previous signal values [OK]

Common Mistakes:

• Using separate clocks for edge detection
• Ignoring previous signal value
• Assigning edge_detected based only on current signal