Debouncer circuit in VHDL - Step-by-Step Execution

Concept Flow - Debouncer circuit

Input: Noisy Button Signal

↓

Sample Input at Clock Edge

↓

Check if Input Stable

↓

Update Output

↓

Output Clean Signal

The debouncer samples the noisy input at each clock cycle, checks if the input is stable, and only updates the output when stable to avoid glitches.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Debouncer is
  Port ( clk : in STD_LOGIC;
         noisy_in : in STD_LOGIC;
         clean_out : out STD_LOGIC);
end Debouncer;

This VHDL code defines a debouncer entity that cleans a noisy button input signal using a clock.

Execution Table

Step	Clock Cycle	Noisy Input	Stable Counter	Condition (Stable?)	Output (clean_out)
1	clk rising edge 1	0	0	No (input changed)	0
2	clk rising edge 2	1	0	No (input changed)	0
3	clk rising edge 3	1	1	No (need more stable cycles)	0
4	clk rising edge 4	1	2	No (need more stable cycles)	0
5	clk rising edge 5	1	3	Yes (stable)	1
6	clk rising edge 6	0	0	No (input changed)	1
7	clk rising edge 7	0	1	No (need more stable cycles)	1
8	clk rising edge 8	0	2	No (need more stable cycles)	1
9	clk rising edge 9	0	3	Yes (stable reached)	0

💡 After stable counter reaches threshold (3), output updates; input changes reset counter.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9
noisy_in	0	0	1	1	1	1	0	0	0	0
stable_counter	0	0	0	1	2	3	0	1	2	3
clean_out	0	0	0	0	0	1	1	1	1	0

Key Moments - 2 Insights

Why does the stable_counter reset to 0 when the noisy input changes?

Because the input is not stable anymore, the counter resets to ensure output only changes after stable input, as shown in steps 6 and 7 in the execution_table.

Why does the output clean_out not change immediately when noisy_in changes?

The output only updates after the input stays stable for enough clock cycles (stable_counter reaches 3), preventing glitches, as seen between steps 2 to 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of stable_counter at clock cycle 3?

A 2

B 3

C 1

D 0

💡 Hint

Check the stable_counter column at step 3 in the execution_table.

At which clock cycle does clean_out first change from 0 to 1?

A Clock cycle 5

B Clock cycle 3

C Clock cycle 4

D Clock cycle 2

💡 Hint

Look at the clean_out column in the execution_table and find when it changes to 1.

If the stable_counter threshold was 2 instead of 3, at which clock cycle would clean_out first become 1?

A Clock cycle 3

B Clock cycle 4

C Clock cycle 2

D Clock cycle 5

💡 Hint

Consider when stable_counter reaches 2 in the execution_table and relate to output change.

Concept Snapshot

Debouncer circuit in VHDL:
- Samples noisy input at clock edges
- Uses a stable counter to track input stability
- Updates output only after input is stable for threshold cycles
- Prevents glitches from noisy button presses
- Typical threshold is 3 stable cycles

Full Transcript

This visual execution shows how a debouncer circuit in VHDL works by sampling a noisy button input at each clock cycle. The stable_counter variable increments when the input stays the same and resets when it changes. Only when the stable_counter reaches a threshold (3 cycles here) does the output clean_out update to the stable input value. This prevents the output from changing immediately on noisy input changes, avoiding glitches. The execution table traces each clock cycle, showing input, counter, condition, and output values. Key moments clarify why the counter resets and why output updates are delayed. The quiz tests understanding of stable_counter values and output changes at specific cycles.

Practice

1.

What is the main purpose of a debouncer circuit in VHDL?

easy

A. To remove noise and glitches from a button input signal

B. To increase the clock speed of the circuit

C. To convert analog signals to digital

D. To store multiple input values simultaneously

Solution

1. Step 1: Understand the problem of noisy inputs

   Mechanical buttons often produce multiple rapid on/off signals (noise) when pressed.

2. Step 2: Role of debouncer circuit

   A debouncer filters this noise to produce a clean, stable signal representing a single press.

3. Final Answer:

   To remove noise and glitches from a button input signal -> Option A

4. Quick Check:

   Debouncer cleans noisy input = A [OK]

Hint: Debouncer cleans noisy button signals to one stable output [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog-to-digital converter
• Assuming debouncer stores multiple inputs

2.

Which of the following is the correct VHDL syntax to declare a signal named counter as a 4-bit unsigned vector?

easy

A. signal counter : std_logic_vector(3 downto 0);

B. signal counter : std_logic_vector(0 to 3);

C. signal counter : unsigned(3 downto 0);

D. signal counter : unsigned(4 downto 0);

Solution

1. Step 1: Understand vector size and type

   A 4-bit vector has indices from 3 downto 0, and unsigned type is used for arithmetic.

2. Step 2: Check each option

   signal counter : unsigned(3 downto 0); correctly declares an unsigned 4-bit vector from 3 downto 0.

3. Final Answer:

   signal counter : unsigned(3 downto 0); -> Option C

4. Quick Check:

   Unsigned 4-bit vector = B [OK]

Hint: Unsigned vectors use (3 downto 0) for 4 bits [OK]

Common Mistakes:

• Using std_logic_vector instead of unsigned for counters
• Incorrect vector range (4 downto 0 is 5 bits)
• Using ascending range (0 to 3) instead of descending

3.

Given the following VHDL snippet for a debouncer process, what will be the value of debounced_out after 10 clock cycles if button_in remains stable at '1'?

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      if counter < 10 then
        counter <= counter + 1;
      else
        debounced_out <= button_in;
      end if;
    else
      counter <= 0;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. '0'

B. '1'

C. Counter value

D. Undefined (signal not assigned)

Solution

1. Step 1: Analyze counter increment and stability

   Since button_in stays '1' and equals last_state, counter increments each clock from 0 to 10 over 10 cycles (while counter < 10).

2. Step 2: Check when debounced_out updates

   debounced_out <= button_in when counter >= 10. On the 10th cycle, counter reaches 10, so debounced_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   After 10 cycles, debounced_out = '1' [OK]

Hint: Output updates only after stable input count reached [OK]

Common Mistakes:

• Assuming output changes immediately on input change
• Confusing counter value with output signal
• Ignoring last_state comparison logic

4.

Identify the error in this VHDL debouncer process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      counter <= counter + 1;
    else
      counter <= 0;
    end if;
    if counter = 10 then
      debounced_out <= button_in;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. button_in is not declared as a signal

B. last_state is updated before counter, causing timing issues

C. debounced_out is assigned outside the clock edge condition

D. Counter is incremented without checking maximum value, causing overflow

Solution

1. Step 1: Check counter increment logic

   Counter increments every clock when input stable but no max limit check, so it can overflow.

2. Step 2: Understand overflow impact

   Without limiting counter, debounced_out may never update correctly or cause unexpected behavior.

3. Final Answer:

   Counter is incremented without checking maximum value, causing overflow -> Option D

4. Quick Check:

   Missing counter max check = overflow risk [OK]

Hint: Always limit counter to max debounce count to avoid overflow [OK]

Common Mistakes:

• Ignoring counter overflow possibility
• Thinking last_state update order causes error
• Assuming debounced_out assignment outside clock edge

5.

You want to design a debouncer that requires the input to be stable for 20ms. Your clock runs at 50MHz. How many clock cycles should the counter count before updating the output?

hard

A. 1,000,000 cycles

B. 1,000 cycles

C. 20,000 cycles

D. 50,000 cycles

Solution

1. Step 1: Calculate clock period

   Clock frequency = 50MHz means period = 1 / 50,000,000 = 20ns per cycle.

2. Step 2: Calculate cycles for 20ms

   20ms = 20,000,000ns. Number of cycles = 20,000,000ns / 20ns = 1,000,000 cycles.

3. Step 3: Re-check calculation

   Wait, 20ms = 0.02 seconds. Clock frequency = 50,000,000 Hz. Cycles = 0.02 * 50,000,000 = 1,000,000 cycles.

4. Final Answer:

   1,000,000 cycles -> Option A

5. Quick Check:

   Stable time * clock freq = cycles [OK]

Hint: Multiply stable time by clock frequency for cycles [OK]

Common Mistakes:

• Confusing ms with us or ns units
• Dividing instead of multiplying time and frequency
• Choosing wrong option due to quick guess