Debouncer circuit in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple debouncer process

What is the output signal debounced after 10 clock cycles if the input noisy toggles every cycle?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Debouncer is
    Port ( clk : in STD_LOGIC;
           noisy : in STD_LOGIC;
           debounced : out STD_LOGIC);
end Debouncer;

architecture Behavioral of Debouncer is
    signal count : integer := 0;
    signal stable_state : STD_LOGIC := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if noisy = stable_state then
                count <= 0;
            else
                count <= count + 1;
                if count = 3 then
                    stable_state <= noisy;
                    count <= 0;
                end if;
            end if;
        end if;
    end process;
    debounced <= stable_state;
end Behavioral;

A '0'

B '1'

C undefined

D toggles every cycle

💡 Hint

Think about how many consecutive cycles the input must be stable before the output changes.

The debouncer waits for 3 consecutive cycles of the input being different before changing the output. Since the input toggles every cycle, it never stays stable for 3 cycles, so the output remains at its initial value '0'.

🧠 Conceptual

intermediate

Purpose of a debouncer circuit

What is the main purpose of a debouncer circuit in digital design?

A To convert analog signals to digital signals

B To filter out rapid, unwanted toggling of a signal caused by mechanical switch bounce

C To increase the clock frequency of a digital system

D To amplify weak digital signals

💡 Hint

Think about what happens when you press a mechanical button.

Mechanical switches often produce multiple rapid on/off signals (bounces) when pressed or released. A debouncer circuit filters these out to produce a clean, stable signal.

🔧 Debug

advanced

Identify the error in this debouncer VHDL code

What error will this VHDL debouncer code produce when synthesized?

VHDL

process(clk)
begin
    if rising_edge(clk) then
        if noisy /= stable_state then
            count <= count + 1;
        else
            count <= 0;
        end if;
        if count = 3 then
            stable_state <= noisy;
            count <= 0;
        end if;
    end if;
end process;

A Synthesis error due to missing initialization of 'count'

B Runtime error due to count overflow

C No error, code synthesizes correctly

D Synthesis error due to multiple drivers on 'stable_state'

💡 Hint

Consider how 'count' is declared and initialized in VHDL.

In VHDL, signals like 'count' must be initialized outside the process or in a reset condition. Without initialization, synthesis tools may report an error.

📝 Syntax

advanced

Correct syntax for a conditional signal assignment in VHDL

Which option correctly assigns 'debounced' to '1' if 'count' is greater than or equal to 3, else '0'?

A debounced := '1' if count >= 3 else '0';

B debounced = '1' when count >= 3 else '0';

C debounced <= '1' when count >= 3 else '0';

D debounced <= if count >= 3 then '1' else '0';

💡 Hint

Remember the VHDL syntax for conditional signal assignment uses 'when ... else'.

Option C uses the correct VHDL syntax for conditional signal assignment. Other options use invalid assignment operators or syntax.

🚀 Application

expert

Number of stable cycles required for debouncing

If a debouncer requires the input signal to be stable for 5 consecutive clock cycles before changing the output, how many clock cycles minimum will it take to reflect a change on the output after the input changes?

A 1 clock cycle

B 5 clock cycles

C 4 clock cycles

D 6 clock cycles

💡 Hint

Consider that the output changes only after the stable count reaches 5, and the count increments after the input change.

The output changes after the input has been stable for 5 full cycles. The count starts at 0 on the first different input cycle, so the output changes on the 6th cycle after the input change.

Practice

1.

What is the main purpose of a debouncer circuit in VHDL?

easy

A. To remove noise and glitches from a button input signal

B. To increase the clock speed of the circuit

C. To convert analog signals to digital

D. To store multiple input values simultaneously

Solution

1. Step 1: Understand the problem of noisy inputs

   Mechanical buttons often produce multiple rapid on/off signals (noise) when pressed.

2. Step 2: Role of debouncer circuit

   A debouncer filters this noise to produce a clean, stable signal representing a single press.

3. Final Answer:

   To remove noise and glitches from a button input signal -> Option A

4. Quick Check:

   Debouncer cleans noisy input = A [OK]

Hint: Debouncer cleans noisy button signals to one stable output [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog-to-digital converter
• Assuming debouncer stores multiple inputs

2.

Which of the following is the correct VHDL syntax to declare a signal named counter as a 4-bit unsigned vector?

easy

A. signal counter : std_logic_vector(3 downto 0);

B. signal counter : std_logic_vector(0 to 3);

C. signal counter : unsigned(3 downto 0);

D. signal counter : unsigned(4 downto 0);

Solution

1. Step 1: Understand vector size and type

   A 4-bit vector has indices from 3 downto 0, and unsigned type is used for arithmetic.

2. Step 2: Check each option

   signal counter : unsigned(3 downto 0); correctly declares an unsigned 4-bit vector from 3 downto 0.

3. Final Answer:

   signal counter : unsigned(3 downto 0); -> Option C

4. Quick Check:

   Unsigned 4-bit vector = B [OK]

Hint: Unsigned vectors use (3 downto 0) for 4 bits [OK]

Common Mistakes:

• Using std_logic_vector instead of unsigned for counters
• Incorrect vector range (4 downto 0 is 5 bits)
• Using ascending range (0 to 3) instead of descending

3.

Given the following VHDL snippet for a debouncer process, what will be the value of debounced_out after 10 clock cycles if button_in remains stable at '1'?

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      if counter < 10 then
        counter <= counter + 1;
      else
        debounced_out <= button_in;
      end if;
    else
      counter <= 0;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. '0'

B. '1'

C. Counter value

D. Undefined (signal not assigned)

Solution

1. Step 1: Analyze counter increment and stability

   Since button_in stays '1' and equals last_state, counter increments each clock from 0 to 10 over 10 cycles (while counter < 10).

2. Step 2: Check when debounced_out updates

   debounced_out <= button_in when counter >= 10. On the 10th cycle, counter reaches 10, so debounced_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   After 10 cycles, debounced_out = '1' [OK]

Hint: Output updates only after stable input count reached [OK]

Common Mistakes:

• Assuming output changes immediately on input change
• Confusing counter value with output signal
• Ignoring last_state comparison logic

4.

Identify the error in this VHDL debouncer process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      counter <= counter + 1;
    else
      counter <= 0;
    end if;
    if counter = 10 then
      debounced_out <= button_in;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. button_in is not declared as a signal

B. last_state is updated before counter, causing timing issues

C. debounced_out is assigned outside the clock edge condition

D. Counter is incremented without checking maximum value, causing overflow

Solution

1. Step 1: Check counter increment logic

   Counter increments every clock when input stable but no max limit check, so it can overflow.

2. Step 2: Understand overflow impact

   Without limiting counter, debounced_out may never update correctly or cause unexpected behavior.

3. Final Answer:

   Counter is incremented without checking maximum value, causing overflow -> Option D

4. Quick Check:

   Missing counter max check = overflow risk [OK]

Hint: Always limit counter to max debounce count to avoid overflow [OK]

Common Mistakes:

• Ignoring counter overflow possibility
• Thinking last_state update order causes error
• Assuming debounced_out assignment outside clock edge

5.

You want to design a debouncer that requires the input to be stable for 20ms. Your clock runs at 50MHz. How many clock cycles should the counter count before updating the output?

hard

A. 1,000,000 cycles

B. 1,000 cycles

C. 20,000 cycles

D. 50,000 cycles

Solution

1. Step 1: Calculate clock period

   Clock frequency = 50MHz means period = 1 / 50,000,000 = 20ns per cycle.

2. Step 2: Calculate cycles for 20ms

   20ms = 20,000,000ns. Number of cycles = 20,000,000ns / 20ns = 1,000,000 cycles.

3. Step 3: Re-check calculation

   Wait, 20ms = 0.02 seconds. Clock frequency = 50,000,000 Hz. Cycles = 0.02 * 50,000,000 = 1,000,000 cycles.

4. Final Answer:

   1,000,000 cycles -> Option A

5. Quick Check:

   Stable time * clock freq = cycles [OK]

Hint: Multiply stable time by clock frequency for cycles [OK]

Common Mistakes:

• Confusing ms with us or ns units
• Dividing instead of multiplying time and frequency
• Choosing wrong option due to quick guess