Debouncer circuit in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the input signal for the button.

VHDL

signal button_input : std_logic := '[1]';

Drag options to blanks, or click blank then click option'

A'0'

B'Z'

C'1'

D'X'

Attempts:

3 left

💡 Hint

Common Mistakes

Using '1' as initial value, which means pressed state.

Using 'Z' or 'X' which are undefined or high impedance.

The button input signal should be initialized to logic '0' to represent a stable low state.

2fill in blank

medium

Complete the code to define the clock process sensitivity list.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- debounce logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bbutton_input

Creset

Dclk, reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using button_input in sensitivity list, which is incorrect for synchronous logic.

Including reset unnecessarily.

The process should be sensitive to the clock signal 'clk' to trigger on clock edges.

3fill in blank

hard

Fix the error in the signal assignment inside the debounce process.

VHDL

if counter = [1] then
  debounced_output <= button_input;
  counter <= 0;
else
  counter <= counter + 1;
end if;

Drag options to blanks, or click blank then click option'

AMAXCOUNT

Bmax_count

CMAX_COUNT

Dmaxcount

Attempts:

3 left

💡 Hint

Common Mistakes

Using lowercase or misspelled constant names causing errors.

Signal names in VHDL are case insensitive but constants are usually declared in uppercase by convention. Using 'MAX_COUNT' matches the constant name.

4fill in blank

hard

Fill both blanks to complete the counter declaration and reset condition.

VHDL

signal counter : [1] := 0;

process(clk, reset)
begin
  if reset = '[2]' then
    counter <= 0;
  elsif rising_edge(clk) then
    -- counter logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Ainteger range 0 to MAX_COUNT

B'1'

C'0'

Dstd_logic_vector(3 downto 0)

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic_vector for counter without conversion.

Checking reset for '0' when it is active high.

The counter is declared as an integer with a range up to MAX_COUNT. The reset condition checks if reset is '1' to clear the counter.

5fill in blank

hard

Fill all three blanks to complete the debouncer output assignment with stable input check.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if button_input = [1] then
      if stable_count = [2] then
        debounced_output <= [3];
        stable_count <= 0;
      else
        stable_count <= stable_count + 1;
      end if;
    else
      stable_count <= 0;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

A'1'

BMAX_STABLE

Cbutton_input

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Checking for '0' instead of '1' for pressed.

Using wrong constant for stable count.

Assigning debounced output to a wrong signal.

The code checks if the button input is '1' (pressed). When the stable count reaches MAX_STABLE, it assigns the debounced output to the current button input value.

Practice

1.

What is the main purpose of a debouncer circuit in VHDL?

easy

A. To remove noise and glitches from a button input signal

B. To increase the clock speed of the circuit

C. To convert analog signals to digital

D. To store multiple input values simultaneously

Solution

1. Step 1: Understand the problem of noisy inputs

   Mechanical buttons often produce multiple rapid on/off signals (noise) when pressed.

2. Step 2: Role of debouncer circuit

   A debouncer filters this noise to produce a clean, stable signal representing a single press.

3. Final Answer:

   To remove noise and glitches from a button input signal -> Option A

4. Quick Check:

   Debouncer cleans noisy input = A [OK]

Hint: Debouncer cleans noisy button signals to one stable output [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog-to-digital converter
• Assuming debouncer stores multiple inputs

2.

Which of the following is the correct VHDL syntax to declare a signal named counter as a 4-bit unsigned vector?

easy

A. signal counter : std_logic_vector(3 downto 0);

B. signal counter : std_logic_vector(0 to 3);

C. signal counter : unsigned(3 downto 0);

D. signal counter : unsigned(4 downto 0);

Solution

1. Step 1: Understand vector size and type

   A 4-bit vector has indices from 3 downto 0, and unsigned type is used for arithmetic.

2. Step 2: Check each option

   signal counter : unsigned(3 downto 0); correctly declares an unsigned 4-bit vector from 3 downto 0.

3. Final Answer:

   signal counter : unsigned(3 downto 0); -> Option C

4. Quick Check:

   Unsigned 4-bit vector = B [OK]

Hint: Unsigned vectors use (3 downto 0) for 4 bits [OK]

Common Mistakes:

• Using std_logic_vector instead of unsigned for counters
• Incorrect vector range (4 downto 0 is 5 bits)
• Using ascending range (0 to 3) instead of descending

3.

Given the following VHDL snippet for a debouncer process, what will be the value of debounced_out after 10 clock cycles if button_in remains stable at '1'?

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      if counter < 10 then
        counter <= counter + 1;
      else
        debounced_out <= button_in;
      end if;
    else
      counter <= 0;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. '0'

B. '1'

C. Counter value

D. Undefined (signal not assigned)

Solution

1. Step 1: Analyze counter increment and stability

   Since button_in stays '1' and equals last_state, counter increments each clock from 0 to 10 over 10 cycles (while counter < 10).

2. Step 2: Check when debounced_out updates

   debounced_out <= button_in when counter >= 10. On the 10th cycle, counter reaches 10, so debounced_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   After 10 cycles, debounced_out = '1' [OK]

Hint: Output updates only after stable input count reached [OK]

Common Mistakes:

• Assuming output changes immediately on input change
• Confusing counter value with output signal
• Ignoring last_state comparison logic

4.

Identify the error in this VHDL debouncer process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if button_in = last_state then
      counter <= counter + 1;
    else
      counter <= 0;
    end if;
    if counter = 10 then
      debounced_out <= button_in;
    end if;
    last_state <= button_in;
  end if;
end process;

medium

A. button_in is not declared as a signal

B. last_state is updated before counter, causing timing issues

C. debounced_out is assigned outside the clock edge condition

D. Counter is incremented without checking maximum value, causing overflow

Solution

1. Step 1: Check counter increment logic

   Counter increments every clock when input stable but no max limit check, so it can overflow.

2. Step 2: Understand overflow impact

   Without limiting counter, debounced_out may never update correctly or cause unexpected behavior.

3. Final Answer:

   Counter is incremented without checking maximum value, causing overflow -> Option D

4. Quick Check:

   Missing counter max check = overflow risk [OK]

Hint: Always limit counter to max debounce count to avoid overflow [OK]

Common Mistakes:

• Ignoring counter overflow possibility
• Thinking last_state update order causes error
• Assuming debounced_out assignment outside clock edge

5.

You want to design a debouncer that requires the input to be stable for 20ms. Your clock runs at 50MHz. How many clock cycles should the counter count before updating the output?

hard

A. 1,000,000 cycles

B. 1,000 cycles

C. 20,000 cycles

D. 50,000 cycles

Solution

1. Step 1: Calculate clock period

   Clock frequency = 50MHz means period = 1 / 50,000,000 = 20ns per cycle.

2. Step 2: Calculate cycles for 20ms

   20ms = 20,000,000ns. Number of cycles = 20,000,000ns / 20ns = 1,000,000 cycles.

3. Step 3: Re-check calculation

   Wait, 20ms = 0.02 seconds. Clock frequency = 50,000,000 Hz. Cycles = 0.02 * 50,000,000 = 1,000,000 cycles.

4. Final Answer:

   1,000,000 cycles -> Option A

5. Quick Check:

   Stable time * clock freq = cycles [OK]

Hint: Multiply stable time by clock frequency for cycles [OK]

Common Mistakes:

• Confusing ms with us or ns units
• Dividing instead of multiplying time and frequency
• Choosing wrong option due to quick guess