Component declaration and instantiation in VHDL - Step-by-Step Execution

Concept Flow - Component declaration and instantiation

Declare Component

↓

Define Ports

↓

Instantiate Component

↓

Map Ports to Signals

↓

Use Component in Architecture

↓

Simulation/Execution

First, declare the component with its ports, then instantiate it inside an architecture by mapping its ports to signals.

Execution Sample

VHDL

component AND_GATE is
  port(a, b: in std_logic; y: out std_logic);
end component;

U1: AND_GATE port map(a => A, b => B, y => Y);

Declares an AND gate component and instantiates it by connecting signals A, B, and Y.

Execution Table

Step	Action	Component/Signal	Port Mapping	Result
1	Declare component	AND_GATE	a, b: in; y: out	Component AND_GATE known with ports a,b,y
2	Instantiate component	U1: AND_GATE	a => A, b => B, y => Y	Instance U1 created with mapped signals
3	Connect signals	A, B, Y	Mapped to ports a, b, y	Signals connected to component ports
4	Use in architecture	U1	N/A	Component U1 active in design
5	Simulation runs	U1	Signals A,B drive a,b; output y drives Y	Output Y reflects AND of A and B
6	End	N/A	N/A	Execution complete

💡 Simulation ends after component output updates based on input signals

Variable Tracker

Signal/Port	Initial	After Instantiation	After Simulation
A	Unknown	Mapped to a	Input value (e.g. '1')
B	Unknown	Mapped to b	Input value (e.g. '0')
Y	Unknown	Mapped to y	Output value (e.g. '0' for AND)
a	N/A	Port of AND_GATE	Reflects A
b	N/A	Port of AND_GATE	Reflects B
y	N/A	Port of AND_GATE	Reflects AND of a and b

Key Moments - 3 Insights

Why do we declare a component before instantiating it?

The declaration tells VHDL what ports the component has so it can check connections during instantiation, as shown in step 1 and 2 of the execution_table.

What happens if port mapping is incorrect?

Incorrect port mapping causes errors or wrong signal connections, because the signals won't match the declared ports, as seen in step 3 where signals connect to ports.

Is the component active immediately after instantiation?

No, the component becomes active when the architecture runs and signals drive the ports, as shown in steps 4 and 5.

Visual Quiz - 3 Questions

Look at the execution_table, at which step is the component instance created?

A Step 2

B Step 1

C Step 4

D Step 5

💡 Hint

Check the 'Action' column for 'Instantiate component' in execution_table row 2

According to variable_tracker, what is the value of signal Y after simulation if inputs A=1 and B=0?

A '1'

B '0'

C 'X' (unknown)

D No value assigned

💡 Hint

Look at the 'After Simulation' column for signal Y in variable_tracker

If port mapping is missing for port 'y', what will happen during simulation?

A Simulation runs normally

B Input signals A and B are ignored

C Error or output Y is not driven

D Component is not instantiated

💡 Hint

Refer to key_moments about port mapping importance and execution_table step 3

Concept Snapshot

Component declaration:
component Name is
  port(...);
end component;

Instantiation:
InstanceName: Name port map(signal => port,...);

Declare first, then instantiate by mapping signals to ports.
This connects reusable blocks inside designs.

Full Transcript

In VHDL, you first declare a component to define its ports. Then you instantiate it inside an architecture by mapping its ports to signals. This allows you to reuse hardware blocks. The execution flow starts with declaration, then instantiation, port mapping, and finally simulation where signals drive the component ports. The variable tracker shows how signals connect to ports and how outputs depend on inputs. Common confusions include why declaration is needed before instantiation, the importance of correct port mapping, and when the component becomes active. The visual quiz tests understanding of these steps and signal values during simulation.

Practice

1. What is the main purpose of a component declaration in VHDL?

easy

A. To declare variables inside a process

B. To create a copy of a block in the design

C. To assign values to signals

D. To define the interface of a reusable block

Solution

1. Step 1: Understand component declaration role

   A component declaration specifies the inputs, outputs, and interface of a reusable block in VHDL.

2. Step 2: Differentiate from instantiation

   Instantiation creates a copy of the component, but declaration only defines its interface.

3. Final Answer:

   To define the interface of a reusable block -> Option D

4. Quick Check:

   Component declaration = interface definition [OK]

Hint: Declaration defines interface; instantiation creates instance [OK]

Common Mistakes:

• Confusing declaration with instantiation
• Thinking declaration assigns signal values
• Mixing component declaration with variable declaration

2. Which of the following is the correct syntax to declare a component named Adder with two inputs A, B and one output Sum of type std_logic_vector(3 downto 0)?

easy

A. component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

B. component Adder is port (A, B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

C. component Adder port (A, B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

D. component Adder is port (A: in std_logic_vector(3 downto 0), B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

Solution

1. Step 1: Check component declaration syntax

   The correct syntax requires the keyword is after the component name and the port list inside parentheses with semicolons separating ports.

2. Step 2: Verify port declarations

   Each port must be declared separately with direction and type. Ports separated by semicolons, not commas.

3. Final Answer:

   component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; -> Option A

4. Quick Check:

   Correct syntax = component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; [OK]

Hint: Use semicolons between ports and include 'is' keyword [OK]

Common Mistakes:

• Omitting 'is' keyword after component name
• Using commas instead of semicolons between ports
• Grouping multiple ports in one declaration incorrectly

3. Given the following component declaration and instantiation, what is the output value of Y after simulation?

component Inverter is
  port (A: in std_logic; Y: out std_logic);
end component;

signal A_sig, Y_sig: std_logic := '0';

U1: Inverter port map (A => A_sig, Y => Y_sig);

-- Assume Inverter outputs the logical NOT of input A
-- Initial A_sig = '0'

medium

A. Undefined (U)

B. '1'

C. '0'

D. Simulation error

Solution

1. Step 1: Understand component behavior

   The Inverter component outputs the logical NOT of input A, so if A is '0', output Y should be '1'.

2. Step 2: Check signal initial value and mapping

   Signal A_sig is initialized to '0' and connected to input A. Therefore, Y_sig will be '1' after simulation.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   NOT '0' = '1' [OK]

Hint: Invert input signal value for output [OK]

Common Mistakes:

• Assuming output equals input without inversion
• Ignoring initial signal values
• Confusing signal names in port map

4. Identify the error in the following component instantiation:

component Counter is
  port (Clk: in std_logic; Count: out integer);
end component;

signal clk_sig: std_logic := '0';
signal count_sig: integer := 0;

U1: Counter port map (Clk => clk_sig, Count => clk_sig);

medium

A. Signal clk_sig is connected to Count port incorrectly

B. Signal count_sig is connected to Count port incorrectly

C. Component declaration missing architecture

D. Signal clk_sig is not initialized

Solution

1. Step 1: Check port map connections

   The Count port expects an integer output, but it is connected to clk_sig, which is std_logic.

2. Step 2: Identify type mismatch

   Connecting a std_logic signal to an integer port causes a type error.

3. Final Answer:

   Signal clk_sig is connected to Count port incorrectly -> Option A

4. Quick Check:

   Port type mismatch = Signal clk_sig is connected to Count port incorrectly [OK]

Hint: Match signal types exactly in port map [OK]

Common Mistakes:

• Connecting signals to wrong ports
• Ignoring signal data types
• Assuming missing architecture causes instantiation error

5. You want to instantiate two identical components named FlipFlop inside an architecture. Each has ports D (input), Q (output), and Clk (input). How do you correctly declare and instantiate both components with separate signals D1, Q1 and D2, Q2 sharing the same clock Clk_sig?

hard

A. Declare component once and instantiate once, connecting all signals to that single instance

B. Declare component twice with different names, then instantiate once with all signals

C. Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig

D. Instantiate component once with arrays D(1 to 2), Q(1 to 2), and connect signals accordingly

Solution

1. Step 1: Declare component once

   In VHDL, a component is declared once to define its interface, regardless of how many instances are created.

2. Step 2: Instantiate component twice with separate signals

   Each instance must have its own port map connecting unique input/output signals (D1/Q1 and D2/Q2), but they can share the same clock signal (Clk_sig).

3. Final Answer:

   Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig -> Option C

4. Quick Check:

   One declaration, multiple instantiations with separate signals [OK]

Hint: Declare once, instantiate multiple times with unique signals [OK]

Common Mistakes:

• Declaring component multiple times unnecessarily
• Instantiating once for multiple signals
• Confusing signal arrays with separate signals