Component declaration and instantiation in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple component instantiation

Given the following VHDL code, what is the output on the signal Y after one clock cycle?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AND_GATE is
  Port ( A : in STD_LOGIC;
         B : in STD_LOGIC;
         Y : out STD_LOGIC);
end AND_GATE;

architecture Behavioral of AND_GATE is
begin
  Y <= A and B;
end Behavioral;

entity TOP is
  Port ( X1 : in STD_LOGIC;
         X2 : in STD_LOGIC;
         Y : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  component AND_GATE
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
  end component;

  signal S1 : STD_LOGIC;
begin
  U1: AND_GATE port map(A => X1, B => X2, Y => S1);
  Y <= S1;
end Structural;

Assume inputs X1 = '1' and X2 = '0'.

A '0'

B '1'

C 'Z'

D 'X'

💡 Hint

Remember that AND operation outputs '1' only if both inputs are '1'.

The AND_GATE component outputs the logical AND of inputs A and B. Since X1='1' and X2='0', the output Y will be '0'.

❓ Predict Output

intermediate

Signal value after component instantiation with multiple signals

Consider the following VHDL snippet. What is the value of signal OUT_SIG after the component OR_GATE is instantiated?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OR_GATE is
  Port ( A : in STD_LOGIC;
         B : in STD_LOGIC;
         Y : out STD_LOGIC);
end OR_GATE;

architecture Behavioral of OR_GATE is
begin
  Y <= A or B;
end Behavioral;

entity TOP is
  Port ( IN1 : in STD_LOGIC;
         IN2 : in STD_LOGIC;
         OUT_SIG : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  component OR_GATE
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
  end component;

  signal TEMP : STD_LOGIC;
begin
  U1: OR_GATE port map(A => IN1, B => IN2, Y => TEMP);
  OUT_SIG <= TEMP;
end Structural;

Inputs are IN1 = '0' and IN2 = '0'.

A 'Z'

B '1'

C '0'

D 'U'

💡 Hint

OR gate outputs '1' if any input is '1'.

Both inputs are '0', so OR operation results in '0'.

❓ Predict Output

advanced

Output of nested component instantiations

Analyze the following VHDL code with nested component instantiations. What is the final output F_OUT?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NOT_GATE is
  Port ( A : in STD_LOGIC;
         Y : out STD_LOGIC);
end NOT_GATE;

architecture Behavioral of NOT_GATE is
begin
  Y <= not A;
end Behavioral;

entity AND_GATE is
  Port ( A : in STD_LOGIC;
         B : in STD_LOGIC;
         Y : out STD_LOGIC);
end AND_GATE;

architecture Behavioral of AND_GATE is
begin
  Y <= A and B;
end Behavioral;

entity TOP is
  Port ( IN1 : in STD_LOGIC;
         IN2 : in STD_LOGIC;
         F_OUT : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  component NOT_GATE
    Port ( A : in STD_LOGIC;
           Y : out STD_LOGIC);
  end component;

  component AND_GATE
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
  end component;

  signal S1, S2 : STD_LOGIC;
begin
  U1: NOT_GATE port map(A => IN1, Y => S1);
  U2: AND_GATE port map(A => S1, B => IN2, Y => S2);
  F_OUT <= S2;
end Structural;

Inputs are IN1 = '0' and IN2 = '1'.

A 'U'

B '0'

C 'Z'

D '1'

💡 Hint

First invert IN1, then AND with IN2.

IN1='0' inverted is '1'. Then '1' AND '1' equals '1'. So F_OUT='1'.

❓ Predict Output

advanced

Error type from incorrect port mapping

What error will occur when compiling the following VHDL code?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BUF_GATE is
  Port ( A : in STD_LOGIC;
         Y : out STD_LOGIC);
end BUF_GATE;

architecture Behavioral of BUF_GATE is
begin
  Y <= A;
end Behavioral;

entity TOP is
  Port ( IN1 : in STD_LOGIC;
         OUT1 : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  component BUF_GATE
    Port ( A : in STD_LOGIC;
           Y : out STD_LOGIC);
  end component;

begin
  U1: BUF_GATE port map(A => IN1, Z => OUT1);
end Structural;

A No error, code compiles and runs correctly

B Compilation error: port 'Z' not found in component BUF_GATE

C Runtime error: signal assignment failure

D Warning: unused port 'Y' in component BUF_GATE

💡 Hint

Check if all port names in port map match the component declaration.

Port map uses 'Z' which is not declared in BUF_GATE component ports, causing a compilation error.

🧠 Conceptual

expert

Number of component instances and signal connections

In a VHDL design, you instantiate a component MY_COMP three times inside an architecture. Each instance connects to a unique signal for output but shares the same input signal. How many unique output signals must be declared in the architecture to avoid signal conflicts?

A 3

B 1

C 2

D 0

💡 Hint

Each component instance output must connect to a separate signal to avoid conflicts.

Each instance drives its own output signal; sharing output signals causes conflicts. So 3 unique output signals are needed.

Practice

1. What is the main purpose of a component declaration in VHDL?

easy

A. To declare variables inside a process

B. To create a copy of a block in the design

C. To assign values to signals

D. To define the interface of a reusable block

Solution

1. Step 1: Understand component declaration role

   A component declaration specifies the inputs, outputs, and interface of a reusable block in VHDL.

2. Step 2: Differentiate from instantiation

   Instantiation creates a copy of the component, but declaration only defines its interface.

3. Final Answer:

   To define the interface of a reusable block -> Option D

4. Quick Check:

   Component declaration = interface definition [OK]

Hint: Declaration defines interface; instantiation creates instance [OK]

Common Mistakes:

• Confusing declaration with instantiation
• Thinking declaration assigns signal values
• Mixing component declaration with variable declaration

2. Which of the following is the correct syntax to declare a component named Adder with two inputs A, B and one output Sum of type std_logic_vector(3 downto 0)?

easy

A. component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

B. component Adder is port (A, B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

C. component Adder port (A, B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

D. component Adder is port (A: in std_logic_vector(3 downto 0), B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

Solution

1. Step 1: Check component declaration syntax

   The correct syntax requires the keyword is after the component name and the port list inside parentheses with semicolons separating ports.

2. Step 2: Verify port declarations

   Each port must be declared separately with direction and type. Ports separated by semicolons, not commas.

3. Final Answer:

   component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; -> Option A

4. Quick Check:

   Correct syntax = component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; [OK]

Hint: Use semicolons between ports and include 'is' keyword [OK]

Common Mistakes:

• Omitting 'is' keyword after component name
• Using commas instead of semicolons between ports
• Grouping multiple ports in one declaration incorrectly

3. Given the following component declaration and instantiation, what is the output value of Y after simulation?

component Inverter is
  port (A: in std_logic; Y: out std_logic);
end component;

signal A_sig, Y_sig: std_logic := '0';

U1: Inverter port map (A => A_sig, Y => Y_sig);

-- Assume Inverter outputs the logical NOT of input A
-- Initial A_sig = '0'

medium

A. Undefined (U)

B. '1'

C. '0'

D. Simulation error

Solution

1. Step 1: Understand component behavior

   The Inverter component outputs the logical NOT of input A, so if A is '0', output Y should be '1'.

2. Step 2: Check signal initial value and mapping

   Signal A_sig is initialized to '0' and connected to input A. Therefore, Y_sig will be '1' after simulation.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   NOT '0' = '1' [OK]

Hint: Invert input signal value for output [OK]

Common Mistakes:

• Assuming output equals input without inversion
• Ignoring initial signal values
• Confusing signal names in port map

4. Identify the error in the following component instantiation:

component Counter is
  port (Clk: in std_logic; Count: out integer);
end component;

signal clk_sig: std_logic := '0';
signal count_sig: integer := 0;

U1: Counter port map (Clk => clk_sig, Count => clk_sig);

medium

A. Signal clk_sig is connected to Count port incorrectly

B. Signal count_sig is connected to Count port incorrectly

C. Component declaration missing architecture

D. Signal clk_sig is not initialized

Solution

1. Step 1: Check port map connections

   The Count port expects an integer output, but it is connected to clk_sig, which is std_logic.

2. Step 2: Identify type mismatch

   Connecting a std_logic signal to an integer port causes a type error.

3. Final Answer:

   Signal clk_sig is connected to Count port incorrectly -> Option A

4. Quick Check:

   Port type mismatch = Signal clk_sig is connected to Count port incorrectly [OK]

Hint: Match signal types exactly in port map [OK]

Common Mistakes:

• Connecting signals to wrong ports
• Ignoring signal data types
• Assuming missing architecture causes instantiation error

5. You want to instantiate two identical components named FlipFlop inside an architecture. Each has ports D (input), Q (output), and Clk (input). How do you correctly declare and instantiate both components with separate signals D1, Q1 and D2, Q2 sharing the same clock Clk_sig?

hard

A. Declare component once and instantiate once, connecting all signals to that single instance

B. Declare component twice with different names, then instantiate once with all signals

C. Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig

D. Instantiate component once with arrays D(1 to 2), Q(1 to 2), and connect signals accordingly

Solution

1. Step 1: Declare component once

   In VHDL, a component is declared once to define its interface, regardless of how many instances are created.

2. Step 2: Instantiate component twice with separate signals

   Each instance must have its own port map connecting unique input/output signals (D1/Q1 and D2/Q2), but they can share the same clock signal (Clk_sig).

3. Final Answer:

   Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig -> Option C

4. Quick Check:

   One declaration, multiple instantiations with separate signals [OK]

Hint: Declare once, instantiate multiple times with unique signals [OK]

Common Mistakes:

• Declaring component multiple times unnecessarily
• Instantiating once for multiple signals
• Confusing signal arrays with separate signals