Component declaration and instantiation in VHDL - Mini Project: Build & Apply

Component Declaration and Instantiation in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. You want to reuse a small logic block called AndGate inside a bigger circuit called TopLevel. This project will guide you to declare the component AndGate and then instantiate it inside TopLevel.

🎯 Goal: Build a VHDL design where you declare a component named AndGate with two inputs and one output, and then instantiate this component inside a top-level architecture.

📋 What You'll Learn

Declare a component named AndGate with ports a, b as inputs and y as output.

Create a top-level entity named TopLevel with ports in1, in2 as inputs and out1 as output.

Instantiate the AndGate component inside the architecture of TopLevel.

Connect the ports of the instantiated component to the top-level ports.

💡 Why This Matters

🌍 Real World

Component declaration and instantiation lets you reuse small circuit blocks inside bigger designs, saving time and making your code organized.

💼 Career

Hardware engineers use component instantiation to build complex digital systems from smaller tested modules, improving design clarity and maintainability.

1

Declare the AndGate component

Write a component declaration named AndGate inside a package or architecture. It should have ports a and b as inputs of type std_logic, and y as output of type std_logic.

VHDL

-- Declare the component AndGate with ports a, b as inputs and y as output
-- Your code here

Hint

Use the component keyword followed by the component name. Inside port(...), list the ports with directions and types.

2

Create the TopLevel entity with ports

Write an entity declaration named TopLevel with ports in1 and in2 as inputs of type std_logic, and out1 as output of type std_logic.

VHDL

component AndGate is
    port(
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end component;

-- Declare the entity TopLevel with ports in1, in2 as inputs and out1 as output
-- Your code here

Hint

Use the entity keyword followed by the entity name. Define ports similarly to the component.

3

Instantiate the AndGate component inside TopLevel architecture

Write the architecture body for TopLevel. Inside it, instantiate the AndGate component with label U1. Connect a to in1, b to in2, and y to out1.

VHDL

component AndGate is
    port(
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end component;

entity TopLevel is
    port(
        in1 : in std_logic;
        in2 : in std_logic;
        out1 : out std_logic
    );
end entity TopLevel;

-- Write architecture for TopLevel and instantiate AndGate with label U1
-- Your code here

Hint

Use architecture keyword with a name like Behavioral. Instantiate the component with a label and use port map to connect ports.

4

Print the final VHDL code

Print the entire VHDL code including the component declaration, entity, and architecture with the component instantiation.

VHDL

component AndGate is
    port(
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end component;

entity TopLevel is
    port(
        in1 : in std_logic;
        in2 : in std_logic;
        out1 : out std_logic
    );
end entity TopLevel;

architecture Behavioral of TopLevel is
begin
    U1: AndGate port map(
        a => in1,
        b => in2,
        y => out1
    );
end Behavioral;

-- Print the full VHDL code below
-- Your code here

Hint

Use report statements to show messages confirming each part is done.

Practice

1. What is the main purpose of a component declaration in VHDL?

easy

A. To declare variables inside a process

B. To create a copy of a block in the design

C. To assign values to signals

D. To define the interface of a reusable block

Solution

1. Step 1: Understand component declaration role

   A component declaration specifies the inputs, outputs, and interface of a reusable block in VHDL.

2. Step 2: Differentiate from instantiation

   Instantiation creates a copy of the component, but declaration only defines its interface.

3. Final Answer:

   To define the interface of a reusable block -> Option D

4. Quick Check:

   Component declaration = interface definition [OK]

Hint: Declaration defines interface; instantiation creates instance [OK]

Common Mistakes:

• Confusing declaration with instantiation
• Thinking declaration assigns signal values
• Mixing component declaration with variable declaration

2. Which of the following is the correct syntax to declare a component named Adder with two inputs A, B and one output Sum of type std_logic_vector(3 downto 0)?

easy

A. component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

B. component Adder is port (A, B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

C. component Adder port (A, B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component;

D. component Adder is port (A: in std_logic_vector(3 downto 0), B: in std_logic_vector(3 downto 0), Sum: out std_logic_vector(3 downto 0)); end component;

Solution

1. Step 1: Check component declaration syntax

   The correct syntax requires the keyword is after the component name and the port list inside parentheses with semicolons separating ports.

2. Step 2: Verify port declarations

   Each port must be declared separately with direction and type. Ports separated by semicolons, not commas.

3. Final Answer:

   component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; -> Option A

4. Quick Check:

   Correct syntax = component Adder is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); Sum: out std_logic_vector(3 downto 0)); end component; [OK]

Hint: Use semicolons between ports and include 'is' keyword [OK]

Common Mistakes:

• Omitting 'is' keyword after component name
• Using commas instead of semicolons between ports
• Grouping multiple ports in one declaration incorrectly

3. Given the following component declaration and instantiation, what is the output value of Y after simulation?

component Inverter is
  port (A: in std_logic; Y: out std_logic);
end component;

signal A_sig, Y_sig: std_logic := '0';

U1: Inverter port map (A => A_sig, Y => Y_sig);

-- Assume Inverter outputs the logical NOT of input A
-- Initial A_sig = '0'

medium

A. Undefined (U)

B. '1'

C. '0'

D. Simulation error

Solution

1. Step 1: Understand component behavior

   The Inverter component outputs the logical NOT of input A, so if A is '0', output Y should be '1'.

2. Step 2: Check signal initial value and mapping

   Signal A_sig is initialized to '0' and connected to input A. Therefore, Y_sig will be '1' after simulation.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   NOT '0' = '1' [OK]

Hint: Invert input signal value for output [OK]

Common Mistakes:

• Assuming output equals input without inversion
• Ignoring initial signal values
• Confusing signal names in port map

4. Identify the error in the following component instantiation:

component Counter is
  port (Clk: in std_logic; Count: out integer);
end component;

signal clk_sig: std_logic := '0';
signal count_sig: integer := 0;

U1: Counter port map (Clk => clk_sig, Count => clk_sig);

medium

A. Signal clk_sig is connected to Count port incorrectly

B. Signal count_sig is connected to Count port incorrectly

C. Component declaration missing architecture

D. Signal clk_sig is not initialized

Solution

1. Step 1: Check port map connections

   The Count port expects an integer output, but it is connected to clk_sig, which is std_logic.

2. Step 2: Identify type mismatch

   Connecting a std_logic signal to an integer port causes a type error.

3. Final Answer:

   Signal clk_sig is connected to Count port incorrectly -> Option A

4. Quick Check:

   Port type mismatch = Signal clk_sig is connected to Count port incorrectly [OK]

Hint: Match signal types exactly in port map [OK]

Common Mistakes:

• Connecting signals to wrong ports
• Ignoring signal data types
• Assuming missing architecture causes instantiation error

5. You want to instantiate two identical components named FlipFlop inside an architecture. Each has ports D (input), Q (output), and Clk (input). How do you correctly declare and instantiate both components with separate signals D1, Q1 and D2, Q2 sharing the same clock Clk_sig?

hard

A. Declare component once and instantiate once, connecting all signals to that single instance

B. Declare component twice with different names, then instantiate once with all signals

C. Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig

D. Instantiate component once with arrays D(1 to 2), Q(1 to 2), and connect signals accordingly

Solution

1. Step 1: Declare component once

   In VHDL, a component is declared once to define its interface, regardless of how many instances are created.

2. Step 2: Instantiate component twice with separate signals

   Each instance must have its own port map connecting unique input/output signals (D1/Q1 and D2/Q2), but they can share the same clock signal (Clk_sig).

3. Final Answer:

   Declare component once, then instantiate twice with different port maps connecting D1/Q1 and D2/Q2 to each instance, sharing Clk_sig -> Option C

4. Quick Check:

   One declaration, multiple instantiations with separate signals [OK]

Hint: Declare once, instantiate multiple times with unique signals [OK]

Common Mistakes:

• Declaring component multiple times unnecessarily
• Instantiating once for multiple signals
• Confusing signal arrays with separate signals