Clock domain considerations in VHDL - Step-by-Step Execution

Concept Flow - Clock domain considerations

Start: Signal in Clock Domain A

↓

Cross to Clock Domain B

↓

Use Synchronizer (e.g., 2 flip-flops)

↓

Check for Metastability

↓

Safe Signal in Clock Domain B

↓

Proceed with Logic in Domain B

Signals crossing from one clock domain to another must be synchronized to avoid errors caused by timing differences.

Execution Sample

VHDL

process(clk_b) is
begin
  if rising_edge(clk_b) then
    sync_1 <= async_signal;
    sync_2 <= sync_1;
  end if;
end process;

This code synchronizes an asynchronous signal from another clock domain into clk_b domain using two flip-flops.

Execution Table

Step	clk_b edge	async_signal	sync_1	sync_2	Action
1	rising	0	0	0	Initial state, no change
2	rising	1	1	0	sync_1 captures async_signal=1
3	rising	1	1	1	sync_2 captures sync_1=1, signal synchronized
4	rising	0	0	1	sync_1 captures async_signal=0
5	rising	0	0	0	sync_2 captures sync_1=0, signal synchronized
6	rising	1	1	0	sync_1 captures async_signal=1
7	rising	1	1	1	sync_2 captures sync_1=1, signal synchronized

💡 Process continues indefinitely on each rising edge of clk_b, synchronizing async_signal.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
async_signal	0	0	1	1	0	0	1	1
sync_1	0	0	1	1	0	0	1	1
sync_2	0	0	0	1	1	0	0	1

Key Moments - 3 Insights

Why do we use two flip-flops (sync_1 and sync_2) instead of just one?

Using two flip-flops reduces the chance of metastability propagating into the receiving clock domain, as shown in steps 2 and 3 where sync_2 stabilizes the signal after sync_1 captures it.

What happens if we read async_signal directly without synchronization?

Reading async_signal directly can cause unpredictable behavior due to timing differences between clock domains, which is why the process uses sync_1 and sync_2 to safely transfer the signal.

Why does sync_2 lag one clock cycle behind sync_1?

sync_2 captures the value of sync_1 on the next rising edge of clk_b, so it always updates one cycle later, ensuring the signal is stable before use.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of sync_2 at step 3?

A 1

B 0

C Undefined

D Same as async_signal

💡 Hint

Check the 'sync_2' column in row with Step=3 in the execution_table.

At which step does sync_1 first capture async_signal=1?

A Step 1

B Step 3

C Step 2

D Step 4

💡 Hint

Look at the 'sync_1' and 'async_signal' columns in the execution_table rows.

If we remove sync_2 flip-flop, what risk increases?

A Signal delay decreases

B Metastability risk increases

C Signal becomes asynchronous

D No change

💡 Hint

Refer to key_moments explanation about using two flip-flops to reduce metastability.

Concept Snapshot

Clock domain crossing requires synchronizers.
Use at least two flip-flops in the receiving clock domain.
This reduces metastability risk.
Signals must be stable before use.
Direct asynchronous reads cause errors.

Full Transcript

When signals move between different clock domains in VHDL, timing differences can cause errors called metastability. To avoid this, we use a synchronizer made of two flip-flops in the receiving clock domain. The first flip-flop captures the asynchronous signal, and the second flip-flop stabilizes it before the signal is used. This process repeats on every rising edge of the receiving clock. Using two flip-flops reduces the chance that unstable signals cause problems. Directly reading asynchronous signals without synchronization can cause unpredictable behavior. The example code shows how to implement this with a process triggered by the receiving clock. The execution table traces how the signal moves through the flip-flops step-by-step.

Practice

1. Why is it important to use synchronizers when signals cross different clock domains in VHDL?

easy

A. To reduce power consumption of the circuit

B. To increase the clock frequency of the receiving domain

C. To prevent metastability and ensure reliable data transfer

D. To simplify the VHDL code syntax

Solution

1. Step 1: Understand metastability in clock domain crossing

   When a signal changes asynchronously between two clock domains, the receiving flip-flop can enter an unstable state called metastability.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to reduce the chance of metastability affecting the receiving domain, ensuring reliable data transfer.

3. Final Answer:

   To prevent metastability and ensure reliable data transfer -> Option C

4. Quick Check:

   Synchronizers prevent metastability = C [OK]

Hint: Synchronizers prevent unstable signals crossing clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Assuming synchronizers reduce power
• Believing synchronizers simplify code syntax

2. Which of the following VHDL code snippets correctly implements a 2-stage synchronizer for a single-bit signal async_sig crossing into clk domain?

easy

A. process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

B. process(clk) begin if rising_edge(clk) then sync2 <= async_sig; sync1 <= sync2; end if; end process;

C. process(clk) begin if falling_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

D. process(clk) begin if rising_edge(clk) then sync1 <= sync2; sync2 <= async_sig; end if; end process;

Solution

1. Step 1: Identify correct flip-flop sequence

   The first flip-flop captures the asynchronous signal, the second flip-flop captures the first flip-flop's output.

2. Step 2: Check clock edge and assignment order

   Using rising_edge(clk) is standard, and assignments must be in order: sync1 <= async_sig; sync2 <= sync1;

3. Final Answer:

   process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process; -> Option A

4. Quick Check:

   Correct order and clock edge = A [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Swapping sync1 and sync2 assignments
• Using falling_edge instead of rising_edge
• Assigning signals in wrong order

3. Given the following VHDL code snippet crossing clock domains, what is the expected behavior of sync2 signal after several clock cycles?

signal async_sig : std_logic;
signal sync1, sync2 : std_logic;

process(clk) begin
  if rising_edge(clk) then
    sync1 <= async_sig;
    sync2 <= sync1;
  end if;
end process;

medium

A. sync2 will immediately match async_sig with no delay

B. sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles

C. sync2 will always be the inverse of async_sig

D. sync2 will cause a runtime error due to signal conflict

Solution

1. Step 1: Understand signal propagation through flip-flops

   sync1 captures async_sig at rising edge, sync2 captures sync1 at next rising edge, causing a two-cycle delay.

2. Step 2: Resulting behavior of sync2

   sync2 becomes a stable, synchronized version of async_sig delayed by two clock cycles, reducing metastability risk.

3. Final Answer:

   sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles -> Option B

4. Quick Check:

   Two flip-flop delay = stable sync2 = A [OK]

Hint: Two flip-flops add two clock cycle delay for stable sync [OK]

Common Mistakes:

• Expecting no delay in sync2
• Thinking sync2 inverts async_sig
• Assuming runtime errors from this code

4. Identify the problem in this VHDL code snippet intended to synchronize a single-bit signal async_sig crossing into clk domain:

process(clk) begin
  if rising_edge(clk) then
    sync2 <= async_sig;
    sync1 <= sync2;
  end if;
end process;

medium

A. The signals sync1 and sync2 are not declared

B. The clock edge should be falling_edge(clk) instead of rising_edge(clk)

C. The process is missing a reset signal

D. The assignments are reversed; sync1 should capture async_sig first

Solution

1. Step 1: Analyze assignment order in process

   sync2 is assigned async_sig first, then sync1 is assigned sync2, which reverses the intended synchronizer chain.

2. Step 2: Correct synchronizer order

   Proper synchronizer assigns sync1 <= async_sig; then sync2 <= sync1; to ensure correct data flow and metastability reduction.

3. Final Answer:

   The assignments are reversed; sync1 should capture async_sig first -> Option D

4. Quick Check:

   Assignment order matters = reversed order = D [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Changing clock edge unnecessarily
• Assuming reset is mandatory here
• Ignoring signal declarations

5. You need to transfer an 8-bit data bus async_data from an asynchronous clock domain to a clk domain in VHDL. Which method is the safest and most reliable to avoid data corruption?

hard

A. Use a handshake protocol with ready/acknowledge signals between domains

B. Use a single 2-stage synchronizer on each bit of the data bus

C. Directly assign async_data to a register in the clk domain

D. Use a combinational logic block to pass data asynchronously

Solution

1. Step 1: Understand complexity of multi-bit data crossing clock domains

   Multi-bit data can change asynchronously, causing partial updates and data corruption if not handled carefully.

2. Step 2: Choose proper synchronization method

   Handshake protocols with ready/acknowledge signals ensure data is stable and fully transferred before use, avoiding corruption.

3. Final Answer:

   Use a handshake protocol with ready/acknowledge signals between domains -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit transfer = B [OK]

Hint: Use handshake or FIFO for multi-bit async data transfer [OK]

Common Mistakes:

• Using single-bit synchronizers on multi-bit buses
• Direct asynchronous assignments causing glitches
• Relying on combinational logic for async crossing