Clock domain considerations in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this clock domain crossing synchronizer?

Consider a 2-flip-flop synchronizer used to transfer a signal from an asynchronous clock domain to a synchronous clock domain. What will be the value of sync_out after 3 rising edges of clk_sync if async_in is held high?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sync is
  Port ( clk_sync : in STD_LOGIC;
         async_in : in STD_LOGIC;
         sync_out : out STD_LOGIC);
end sync;

architecture Behavioral of sync is
  signal ff1, ff2 : STD_LOGIC := '0';
begin
  process(clk_sync)
  begin
    if rising_edge(clk_sync) then
      ff1 <= async_in;
      ff2 <= ff1;
    end if;
  end process;
  sync_out <= ff2;
end Behavioral;

A Undefined (signal glitch)

B '0'

C Signal toggles between '0' and '1'

D '1'

💡 Hint

Think about how the signal propagates through two flip-flops synchronized by the clock.

The signal async_in is sampled by ff1 on the first rising edge, then ff2 samples ff1 on the next rising edge. After 3 rising edges, ff2 will have the stable value '1'.

🧠 Conceptual

intermediate

What is the main purpose of using a synchronizer in clock domain crossing?

Why do we use synchronizers when transferring signals between different clock domains?

A To prevent metastability and ensure stable signal transfer

B To increase the clock frequency in the receiving domain

C To convert analog signals to digital signals

D To reduce power consumption in the clock domain

💡 Hint

Think about what happens when signals cross clock domains asynchronously.

Synchronizers help prevent metastability by allowing signals to settle before being used in the receiving clock domain, ensuring stable and reliable data transfer.

🔧 Debug

advanced

Identify the problem in this clock domain crossing code snippet

Examine the following VHDL code snippet intended to transfer a signal from an asynchronous domain to a synchronous domain. What is the main issue?

VHDL

process(clk_sync)
begin
  if rising_edge(clk_sync) then
    sync_out <= async_in;
  end if;
end process;

A Signal async_in is not declared

B No synchronizer flip-flops; direct assignment causes metastability

C Incorrect clock edge used for sampling

D Missing reset signal for flip-flops

💡 Hint

Think about what happens if you sample an asynchronous signal directly with one flip-flop.

Directly assigning async_in to sync_out on the clock edge without using a synchronizer flip-flop chain can cause metastability and unreliable behavior.

📝 Syntax

advanced

Which VHDL code correctly implements a 2-stage synchronizer?

Choose the VHDL code snippet that correctly implements a 2-flip-flop synchronizer for an asynchronous input signal async_in synchronized to clk_sync.

A

process(clk_sync)
begin
  if rising_edge(clk_sync) then
    ff1 <= async_in;
    ff2 <= ff1;
  end if;
end process;
sync_out <= ff2;

B

process(clk_sync)
begin
  if rising_edge(clk_sync) then
    ff1 <= async_in;
  end if;
end process;
sync_out <= ff1;

C

process(clk_sync)
begin
  if rising_edge(clk_sync) then
    ff2 <= async_in;
    ff1 <= ff2;
  end if;
end process;
sync_out <= ff1;

D

process(clk_sync)
begin
  if rising_edge(clk_sync) then
    ff1 <= ff2;
    ff2 <= async_in;
  end if;
end process;
sync_out <= ff1;

💡 Hint

Remember the order of flip-flops in a synchronizer chain.

Option A correctly samples async_in into ff1 and then transfers ff1 to ff2 on the next clock edge, producing a stable synchronized output.

🚀 Application

expert

How many flip-flops are needed to reduce metastability risk below a threshold?

A design requires that the probability of metastability causing an error is less than 1 in 10⁹. Given the metastability resolution time constant τ and clock period T, how many synchronizer flip-flops n are needed if the probability is approximated by P = e^(-n * T / τ)?

Choose the smallest integer n that satisfies P < 10-9 with T / τ = 5.

A 3

B 4

C 5

D 6

💡 Hint

Use the inequality e^(-n * 5) < 10^-9 and solve for n.

Taking natural logs: -n * 5 < ln(10^-9) = -9 * ln(10). So n > (9 * ln(10)) / 5 ≈ 4.15. The smallest integer satisfying this is 5.

Practice

1. Why is it important to use synchronizers when signals cross different clock domains in VHDL?

easy

A. To reduce power consumption of the circuit

B. To increase the clock frequency of the receiving domain

C. To prevent metastability and ensure reliable data transfer

D. To simplify the VHDL code syntax

Solution

1. Step 1: Understand metastability in clock domain crossing

   When a signal changes asynchronously between two clock domains, the receiving flip-flop can enter an unstable state called metastability.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to reduce the chance of metastability affecting the receiving domain, ensuring reliable data transfer.

3. Final Answer:

   To prevent metastability and ensure reliable data transfer -> Option C

4. Quick Check:

   Synchronizers prevent metastability = C [OK]

Hint: Synchronizers prevent unstable signals crossing clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Assuming synchronizers reduce power
• Believing synchronizers simplify code syntax

2. Which of the following VHDL code snippets correctly implements a 2-stage synchronizer for a single-bit signal async_sig crossing into clk domain?

easy

A. process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

B. process(clk) begin if rising_edge(clk) then sync2 <= async_sig; sync1 <= sync2; end if; end process;

C. process(clk) begin if falling_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

D. process(clk) begin if rising_edge(clk) then sync1 <= sync2; sync2 <= async_sig; end if; end process;

Solution

1. Step 1: Identify correct flip-flop sequence

   The first flip-flop captures the asynchronous signal, the second flip-flop captures the first flip-flop's output.

2. Step 2: Check clock edge and assignment order

   Using rising_edge(clk) is standard, and assignments must be in order: sync1 <= async_sig; sync2 <= sync1;

3. Final Answer:

   process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process; -> Option A

4. Quick Check:

   Correct order and clock edge = A [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Swapping sync1 and sync2 assignments
• Using falling_edge instead of rising_edge
• Assigning signals in wrong order

3. Given the following VHDL code snippet crossing clock domains, what is the expected behavior of sync2 signal after several clock cycles?

signal async_sig : std_logic;
signal sync1, sync2 : std_logic;

process(clk) begin
  if rising_edge(clk) then
    sync1 <= async_sig;
    sync2 <= sync1;
  end if;
end process;

medium

A. sync2 will immediately match async_sig with no delay

B. sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles

C. sync2 will always be the inverse of async_sig

D. sync2 will cause a runtime error due to signal conflict

Solution

1. Step 1: Understand signal propagation through flip-flops

   sync1 captures async_sig at rising edge, sync2 captures sync1 at next rising edge, causing a two-cycle delay.

2. Step 2: Resulting behavior of sync2

   sync2 becomes a stable, synchronized version of async_sig delayed by two clock cycles, reducing metastability risk.

3. Final Answer:

   sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles -> Option B

4. Quick Check:

   Two flip-flop delay = stable sync2 = A [OK]

Hint: Two flip-flops add two clock cycle delay for stable sync [OK]

Common Mistakes:

• Expecting no delay in sync2
• Thinking sync2 inverts async_sig
• Assuming runtime errors from this code

4. Identify the problem in this VHDL code snippet intended to synchronize a single-bit signal async_sig crossing into clk domain:

process(clk) begin
  if rising_edge(clk) then
    sync2 <= async_sig;
    sync1 <= sync2;
  end if;
end process;

medium

A. The signals sync1 and sync2 are not declared

B. The clock edge should be falling_edge(clk) instead of rising_edge(clk)

C. The process is missing a reset signal

D. The assignments are reversed; sync1 should capture async_sig first

Solution

1. Step 1: Analyze assignment order in process

   sync2 is assigned async_sig first, then sync1 is assigned sync2, which reverses the intended synchronizer chain.

2. Step 2: Correct synchronizer order

   Proper synchronizer assigns sync1 <= async_sig; then sync2 <= sync1; to ensure correct data flow and metastability reduction.

3. Final Answer:

   The assignments are reversed; sync1 should capture async_sig first -> Option D

4. Quick Check:

   Assignment order matters = reversed order = D [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Changing clock edge unnecessarily
• Assuming reset is mandatory here
• Ignoring signal declarations

5. You need to transfer an 8-bit data bus async_data from an asynchronous clock domain to a clk domain in VHDL. Which method is the safest and most reliable to avoid data corruption?

hard

A. Use a handshake protocol with ready/acknowledge signals between domains

B. Use a single 2-stage synchronizer on each bit of the data bus

C. Directly assign async_data to a register in the clk domain

D. Use a combinational logic block to pass data asynchronously

Solution

1. Step 1: Understand complexity of multi-bit data crossing clock domains

   Multi-bit data can change asynchronously, causing partial updates and data corruption if not handled carefully.

2. Step 2: Choose proper synchronization method

   Handshake protocols with ready/acknowledge signals ensure data is stable and fully transferred before use, avoiding corruption.

3. Final Answer:

   Use a handshake protocol with ready/acknowledge signals between domains -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit transfer = B [OK]

Hint: Use handshake or FIFO for multi-bit async data transfer [OK]

Common Mistakes:

• Using single-bit synchronizers on multi-bit buses
• Direct asynchronous assignments causing glitches
• Relying on combinational logic for async crossing