Clock domain considerations in VHDL - Mini Project: Build & Apply

Clock Domain Crossing Safety Check in VHDL

📖 Scenario: In digital circuits, signals often move between different clock domains. This can cause errors if not handled carefully. We will create a simple VHDL design to safely transfer a signal from one clock domain to another using a two-stage synchronizer.

🎯 Goal: Build a VHDL module that safely transfers a signal from a source clock domain to a destination clock domain using a two-flip-flop synchronizer to avoid metastability issues.

📋 What You'll Learn

Create a signal in the source clock domain

Define two clock signals: clk_src and clk_dst

Implement a two-stage synchronizer for the signal crossing from clk_src to clk_dst

Output the synchronized signal in the destination clock domain

💡 Why This Matters

🌍 Real World

In real digital circuits, signals often cross from one clock domain to another. Without proper synchronization, this can cause unpredictable behavior. Using a two-stage synchronizer is a common way to safely transfer single-bit signals between clock domains.

💼 Career

Understanding clock domain crossing and synchronization is essential for FPGA and ASIC designers to ensure reliable hardware operation and avoid subtle bugs in digital systems.

1

Define clock signals and source signal

Create two clock signals called clk_src and clk_dst as inputs, and a signal called data_src of type std_logic in the source clock domain.

VHDL

-- Declare 'clk_src', 'clk_dst' as inputs and 'data_src' as a signal
-- Your code here

Hint

Define clk_src, clk_dst, and data_src as inputs in the entity.

2

Add signals for synchronizer stages

Inside the architecture, declare two signals called sync_stage1 and sync_stage2 of type std_logic to hold the intermediate synchronization stages.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity clk_domain_example is
    port(
        clk_src : in std_logic;
        clk_dst : in std_logic;
        data_src : in std_logic
    );
end entity;

architecture rtl of clk_domain_example is
    signal sync_stage1 : std_logic;
    signal sync_stage2 : std_logic;
    -- Your code here
begin
    -- No logic yet
end rtl;

Hint

Declare two signals inside the architecture for the synchronizer flip-flops.

3

Implement two-stage synchronizer process

Write a process triggered on the rising edge of clk_dst that assigns sync_stage1 to the input data_src and then assigns sync_stage2 to sync_stage1. This creates the two-stage synchronizer.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity clk_domain_example is
    port(
        clk_src : in std_logic;
        clk_dst : in std_logic;
        data_src : in std_logic
    );
end entity;

architecture rtl of clk_domain_example is
    signal sync_stage1 : std_logic;
    signal sync_stage2 : std_logic;
begin
    process(clk_dst)
    begin
        if rising_edge(clk_dst) then
            -- Your code here
        end if;
    end process;
end rtl;

Hint

Use a process triggered by clk_dst rising edge to assign the two synchronizer stages.

4

Output the synchronized signal

Add an output port called data_dst of type std_logic and assign it to sync_stage2 so the synchronized signal is available outside the module. Then write a concurrent assignment to connect data_dst to sync_stage2.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity clk_domain_example is
    port(
        clk_src : in std_logic;
        clk_dst : in std_logic;
        data_src : in std_logic;
        data_dst : out std_logic
    );
end entity;

architecture rtl of clk_domain_example is
    signal sync_stage1 : std_logic;
    signal sync_stage2 : std_logic;
begin
    process(clk_dst)
    begin
        if rising_edge(clk_dst) then
            sync_stage1 <= data_src;
            sync_stage2 <= sync_stage1;
        end if;
    end process;

    data_dst <= sync_stage2;  -- Your code here
end rtl;

Hint

Add data_dst as an output port and assign it to the last synchronizer stage.

Practice

1. Why is it important to use synchronizers when signals cross different clock domains in VHDL?

easy

A. To reduce power consumption of the circuit

B. To increase the clock frequency of the receiving domain

C. To prevent metastability and ensure reliable data transfer

D. To simplify the VHDL code syntax

Solution

1. Step 1: Understand metastability in clock domain crossing

   When a signal changes asynchronously between two clock domains, the receiving flip-flop can enter an unstable state called metastability.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to reduce the chance of metastability affecting the receiving domain, ensuring reliable data transfer.

3. Final Answer:

   To prevent metastability and ensure reliable data transfer -> Option C

4. Quick Check:

   Synchronizers prevent metastability = C [OK]

Hint: Synchronizers prevent unstable signals crossing clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Assuming synchronizers reduce power
• Believing synchronizers simplify code syntax

2. Which of the following VHDL code snippets correctly implements a 2-stage synchronizer for a single-bit signal async_sig crossing into clk domain?

easy

A. process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

B. process(clk) begin if rising_edge(clk) then sync2 <= async_sig; sync1 <= sync2; end if; end process;

C. process(clk) begin if falling_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

D. process(clk) begin if rising_edge(clk) then sync1 <= sync2; sync2 <= async_sig; end if; end process;

Solution

1. Step 1: Identify correct flip-flop sequence

   The first flip-flop captures the asynchronous signal, the second flip-flop captures the first flip-flop's output.

2. Step 2: Check clock edge and assignment order

   Using rising_edge(clk) is standard, and assignments must be in order: sync1 <= async_sig; sync2 <= sync1;

3. Final Answer:

   process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process; -> Option A

4. Quick Check:

   Correct order and clock edge = A [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Swapping sync1 and sync2 assignments
• Using falling_edge instead of rising_edge
• Assigning signals in wrong order

3. Given the following VHDL code snippet crossing clock domains, what is the expected behavior of sync2 signal after several clock cycles?

signal async_sig : std_logic;
signal sync1, sync2 : std_logic;

process(clk) begin
  if rising_edge(clk) then
    sync1 <= async_sig;
    sync2 <= sync1;
  end if;
end process;

medium

A. sync2 will immediately match async_sig with no delay

B. sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles

C. sync2 will always be the inverse of async_sig

D. sync2 will cause a runtime error due to signal conflict

Solution

1. Step 1: Understand signal propagation through flip-flops

   sync1 captures async_sig at rising edge, sync2 captures sync1 at next rising edge, causing a two-cycle delay.

2. Step 2: Resulting behavior of sync2

   sync2 becomes a stable, synchronized version of async_sig delayed by two clock cycles, reducing metastability risk.

3. Final Answer:

   sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles -> Option B

4. Quick Check:

   Two flip-flop delay = stable sync2 = A [OK]

Hint: Two flip-flops add two clock cycle delay for stable sync [OK]

Common Mistakes:

• Expecting no delay in sync2
• Thinking sync2 inverts async_sig
• Assuming runtime errors from this code

4. Identify the problem in this VHDL code snippet intended to synchronize a single-bit signal async_sig crossing into clk domain:

process(clk) begin
  if rising_edge(clk) then
    sync2 <= async_sig;
    sync1 <= sync2;
  end if;
end process;

medium

A. The signals sync1 and sync2 are not declared

B. The clock edge should be falling_edge(clk) instead of rising_edge(clk)

C. The process is missing a reset signal

D. The assignments are reversed; sync1 should capture async_sig first

Solution

1. Step 1: Analyze assignment order in process

   sync2 is assigned async_sig first, then sync1 is assigned sync2, which reverses the intended synchronizer chain.

2. Step 2: Correct synchronizer order

   Proper synchronizer assigns sync1 <= async_sig; then sync2 <= sync1; to ensure correct data flow and metastability reduction.

3. Final Answer:

   The assignments are reversed; sync1 should capture async_sig first -> Option D

4. Quick Check:

   Assignment order matters = reversed order = D [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Changing clock edge unnecessarily
• Assuming reset is mandatory here
• Ignoring signal declarations

5. You need to transfer an 8-bit data bus async_data from an asynchronous clock domain to a clk domain in VHDL. Which method is the safest and most reliable to avoid data corruption?

hard

A. Use a handshake protocol with ready/acknowledge signals between domains

B. Use a single 2-stage synchronizer on each bit of the data bus

C. Directly assign async_data to a register in the clk domain

D. Use a combinational logic block to pass data asynchronously

Solution

1. Step 1: Understand complexity of multi-bit data crossing clock domains

   Multi-bit data can change asynchronously, causing partial updates and data corruption if not handled carefully.

2. Step 2: Choose proper synchronization method

   Handshake protocols with ready/acknowledge signals ensure data is stable and fully transferred before use, avoiding corruption.

3. Final Answer:

   Use a handshake protocol with ready/acknowledge signals between domains -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit transfer = B [OK]

Hint: Use handshake or FIFO for multi-bit async data transfer [OK]

Common Mistakes:

• Using single-bit synchronizers on multi-bit buses
• Direct asynchronous assignments causing glitches
• Relying on combinational logic for async crossing