Up-down counter with control in VHDL - Step-by-Step Execution

Concept Flow - Up-down counter with control

Start

↓

Check reset?

Yes→Reset counter to 0

No↓

Check control signal

↓

Increment

↓

Output counter

↓

Wait for next clock

↩Back to Check reset?

The counter resets if reset is active, else it checks control to count up or down, then outputs the value and waits for the next clock cycle.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if control = '1' then
      count <= count + 1;
    else
      count <= count - 1;
    end if;
  end if;
end process;

This VHDL process resets the counter or increments/decrements it on each clock rising edge based on the control signal.

Execution Table

Step	reset	clk rising_edge	control	Action	count value
1	0	Yes	1	Increment count	1
2	0	Yes	1	Increment count	2
3	0	Yes	0	Decrement count	1
4	0	Yes	0	Decrement count	0
5	1	Yes	1	Reset count to 0	0
6	0	No	1	No clock edge, no change	0
7	0	Yes	1	Increment count	1

💡 Simulation ends after step 7; counter updated only on rising clock edges and reset.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
count	0	1	2	1	0	0	0	1
reset	0	0	0	0	0	1	0	0
control	1	1	1	0	0	1	1	1
clk rising_edge	No	Yes	Yes	Yes	Yes	Yes	No	Yes

Key Moments - 3 Insights

Why doesn't the count change when reset is '0' but clk rising_edge is 'No' (step 6)?

The counter updates only on the rising edge of the clock. When there is no rising edge, the process does not change the count (see execution_table step 6).

Why does the count reset to 0 at step 5 even though control is '1'?

Reset has the highest priority. When reset is '1', the counter resets immediately regardless of control or clock (execution_table step 5).

How does the control signal affect counting direction?

If control is '1', the counter increments; if '0', it decrements (see steps 1-4 in execution_table).

Visual Quiz - 3 Questions

Look at the execution_table, what is the count value after step 3?

A 1

B 2

C 0

D 3

💡 Hint

Check the 'count value' column at step 3 in the execution_table.

At which step does the reset signal cause the count to reset to 0?

A Step 4

B Step 5

C Step 6

D Step 7

💡 Hint

Look for the step where reset = '1' and count is set to 0 in execution_table.

If control was '0' at step 7, what would the count value be after that step?

A 0

B 2

C -1

D 1

💡 Hint

At step 7, count is 0 before update; control '0' means decrement: 0 - 1 = -1.

Concept Snapshot

VHDL Up-Down Counter with Control:
- On reset='1', count resets to 0 immediately.
- On rising clock edge:
  - If control='1', count increments.
  - Else, count decrements.
- Count updates only on rising clock edges.
- Reset has highest priority.

Full Transcript

This VHDL up-down counter resets the count to zero when the reset signal is active. On each rising edge of the clock, it checks the control signal: if control is '1', it increments the count; if '0', it decrements the count. The counter only updates on clock rising edges, and reset overrides counting. The execution table shows step-by-step how count changes with different reset, clock, and control inputs. Key moments clarify why count doesn't change without clock edge, why reset overrides control, and how control affects counting direction. The visual quiz tests understanding of count values at specific steps and effects of control and reset signals.

Practice

1. What does an up-down counter do in VHDL when the control signal is set to '1'?

easy

A. It counts down by decreasing the value on each clock pulse.

B. It resets the counter to zero immediately.

C. It holds the current count value without change.

D. It counts up by increasing the value on each clock pulse.

Solution

1. Step 1: Understand the control signal meaning

   In an up-down counter, the control signal '1' usually means count up.

2. Step 2: Identify the counting behavior

   When control is '1', the counter increments its value on each clock pulse.

3. Final Answer:

   It counts up by increasing the value on each clock pulse. -> Option D

4. Quick Check:

   Control '1' means count up [OK]

Hint: Control '1' means count up, '0' means count down [OK]

Common Mistakes:

• Confusing control '1' with reset signal
• Thinking control '1' holds the value
• Mixing up count up and count down signals

2. Which of the following is the correct VHDL syntax to declare a 4-bit up-down counter signal named count?

easy

A. signal count : bit_vector(4 downto 1);

B. signal count : std_logic_vector(3 downto 0);

C. signal count : integer range 0 to 15;

D. signal count : std_logic_vector(0 to 3);

Solution

1. Step 1: Identify correct type and range for 4-bit vector

   std_logic_vector(3 downto 0) is the standard way to declare a 4-bit vector from bit 3 down to 0.

2. Step 2: Check other options for errors

   signal count : integer range 0 to 15; uses integer, not vector; signal count : bit_vector(4 downto 1); uses bit_vector with wrong range; signal count : std_logic_vector(0 to 3); uses ascending range which is less common and may cause confusion.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option B

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Incorrect range direction (0 to 3 instead of 3 downto 0)
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a 3-bit up-down counter with control signal up_down and synchronous reset rst, what is the value of count after 3 clock cycles if rst = '0' and up_down = '0' initially?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "000";
    else
      if up_down = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

medium

A. "111"

B. "011"

C. "101"

D. "001"

Solution

1. Step 1: Understand initial conditions and counting direction

   Reset is '0', so no reset occurs. up_down = '0' means count down. Initial count is unknown but assumed 0 at start.

2. Step 2: Calculate count after each clock cycle

   Cycle 1: count = 0 - 1 = 7 (since 3-bit unsigned wraps around)
   Cycle 2: count = 7 - 1 = 6
   Cycle 3: count = 6 - 1 = 5 (binary "101")

3. Final Answer:

   "101" -> Option C

4. Quick Check:

   Counting down 3 times from 0 wraps to 5 [OK]

Hint: Count down wraps around 0 to max value in unsigned [OK]

Common Mistakes:

• Assuming count starts at zero without reset
• Ignoring wrap-around behavior in unsigned counters
• Mixing up count up and count down logic

4. Identify the error in this VHDL snippet for an up-down counter process:

process(clk)
begin
  if clk'event and clk = '1' then
    if rst = '1' then
      count <= (others => '0');
    elsif up_down = '1' then
      count <= count + 1;
    else
      count <= count - 1;
    end if;
  end if;
end process;

medium

A. Using clk'event and clk = '1' instead of rising_edge(clk)

B. Missing asynchronous reset handling

C. Incorrect use of (others => '0') for resetting count

D. No error; code is correct

Solution

1. Step 1: Check clock edge detection method

   Using clk'event and clk = '1' is legal but less safe and less recommended than rising_edge(clk) in modern VHDL.

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for reliable clock detection [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk)
• Confusing synchronous and asynchronous reset
• Incorrect reset assignment syntax

5. You want to design a 4-bit up-down counter in VHDL with a control signal dir where dir = '1' counts up and dir = '0' counts down. The counter should reset to "1000" on reset. Which code snippet correctly implements this behavior inside a synchronous process?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "1000";
    else
      if dir = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

hard

A. Correct implementation for the described behavior.

B. Reset value should be "0000" instead of "1000".

C. Counting direction logic is reversed; dir='1' should count down.

D. Process should use asynchronous reset instead of synchronous.

Solution

1. Step 1: Check reset behavior

   Reset sets count to "1000" as required, synchronously on rising clock edge.

2. Step 2: Verify counting direction logic

   dir='1' triggers count increment, dir='0' triggers decrement, matching the requirement.

3. Step 3: Confirm synchronous reset usage

   Reset is synchronous, which is acceptable and matches the problem statement.

4. Final Answer:

   Correct implementation for the described behavior. -> Option A

5. Quick Check:

   Synchronous reset and correct dir logic [OK]

Hint: Match reset value and dir logic exactly as specified [OK]

Common Mistakes:

• Using wrong reset value
• Reversing count up/down logic
• Confusing synchronous and asynchronous reset