Up-down counter with control in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the clock signal in the entity.

VHDL

entity counter is
  Port (
    clk : [1];
    reset : in std_logic
  );
end counter;

Drag options to blanks, or click blank then click option'

Aout std_logic

Bbuffer std_logic

Cin integer

Din std_logic

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring clock as output instead of input

Using wrong data type like integer

The clock signal should be an input of type std_logic.

2fill in blank

medium

Complete the process sensitivity list to include the clock and reset signals.

VHDL

process([1])
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(clk) then
    -- counting logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Bclk, count

Creset

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Forgetting to include reset in sensitivity list

Including signals that are not needed

The process must be sensitive to both clock and reset signals.

3fill in blank

hard

Fix the error in the counting logic to increment the counter correctly.

VHDL

if up_down = '1' then
  count <= count [1] 1;
else
  count <= count - 1;
end if;

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A+

B*

C-

D/

Attempts:

3 left

💡 Hint

Common Mistakes

Using minus instead of plus for counting up

Using multiplication or division operators

To count up, the counter value must be incremented by adding 1.

4fill in blank

hard

Fill both blanks to complete the conditional check and reset assignment.

VHDL

process(clk, reset)
begin
  if [1] = '1' then
    count <= [2];
  elsif rising_edge(clk) then
    -- counting logic
  end if;
end process;

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Areset

B(others => '0')

C'0'

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Checking wrong signal for reset

Assigning wrong reset value

The reset signal is checked for '1' and the counter is reset to all zeros.

5fill in blank

hard

Fill all three blanks to complete the counter update with control signal.

VHDL

process(clk, reset)
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(clk) then
    if [1] = '1' then
      count <= count [2] 1;
    else
      count <= count [3] 1;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aenable

B+

C-

Dup_down

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong control signal

Mixing up plus and minus operators

The up_down signal controls counting direction: add 1 if '1', subtract 1 if '0'.

Practice

1. What does an up-down counter do in VHDL when the control signal is set to '1'?

easy

A. It counts down by decreasing the value on each clock pulse.

B. It resets the counter to zero immediately.

C. It holds the current count value without change.

D. It counts up by increasing the value on each clock pulse.

Solution

1. Step 1: Understand the control signal meaning

   In an up-down counter, the control signal '1' usually means count up.

2. Step 2: Identify the counting behavior

   When control is '1', the counter increments its value on each clock pulse.

3. Final Answer:

   It counts up by increasing the value on each clock pulse. -> Option D

4. Quick Check:

   Control '1' means count up [OK]

Hint: Control '1' means count up, '0' means count down [OK]

Common Mistakes:

• Confusing control '1' with reset signal
• Thinking control '1' holds the value
• Mixing up count up and count down signals

2. Which of the following is the correct VHDL syntax to declare a 4-bit up-down counter signal named count?

easy

A. signal count : bit_vector(4 downto 1);

B. signal count : std_logic_vector(3 downto 0);

C. signal count : integer range 0 to 15;

D. signal count : std_logic_vector(0 to 3);

Solution

1. Step 1: Identify correct type and range for 4-bit vector

   std_logic_vector(3 downto 0) is the standard way to declare a 4-bit vector from bit 3 down to 0.

2. Step 2: Check other options for errors

   signal count : integer range 0 to 15; uses integer, not vector; signal count : bit_vector(4 downto 1); uses bit_vector with wrong range; signal count : std_logic_vector(0 to 3); uses ascending range which is less common and may cause confusion.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option B

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Incorrect range direction (0 to 3 instead of 3 downto 0)
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a 3-bit up-down counter with control signal up_down and synchronous reset rst, what is the value of count after 3 clock cycles if rst = '0' and up_down = '0' initially?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "000";
    else
      if up_down = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

medium

A. "111"

B. "011"

C. "101"

D. "001"

Solution

1. Step 1: Understand initial conditions and counting direction

   Reset is '0', so no reset occurs. up_down = '0' means count down. Initial count is unknown but assumed 0 at start.

2. Step 2: Calculate count after each clock cycle

   Cycle 1: count = 0 - 1 = 7 (since 3-bit unsigned wraps around)
   Cycle 2: count = 7 - 1 = 6
   Cycle 3: count = 6 - 1 = 5 (binary "101")

3. Final Answer:

   "101" -> Option C

4. Quick Check:

   Counting down 3 times from 0 wraps to 5 [OK]

Hint: Count down wraps around 0 to max value in unsigned [OK]

Common Mistakes:

• Assuming count starts at zero without reset
• Ignoring wrap-around behavior in unsigned counters
• Mixing up count up and count down logic

4. Identify the error in this VHDL snippet for an up-down counter process:

process(clk)
begin
  if clk'event and clk = '1' then
    if rst = '1' then
      count <= (others => '0');
    elsif up_down = '1' then
      count <= count + 1;
    else
      count <= count - 1;
    end if;
  end if;
end process;

medium

A. Using clk'event and clk = '1' instead of rising_edge(clk)

B. Missing asynchronous reset handling

C. Incorrect use of (others => '0') for resetting count

D. No error; code is correct

Solution

1. Step 1: Check clock edge detection method

   Using clk'event and clk = '1' is legal but less safe and less recommended than rising_edge(clk) in modern VHDL.

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for reliable clock detection [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk)
• Confusing synchronous and asynchronous reset
• Incorrect reset assignment syntax

5. You want to design a 4-bit up-down counter in VHDL with a control signal dir where dir = '1' counts up and dir = '0' counts down. The counter should reset to "1000" on reset. Which code snippet correctly implements this behavior inside a synchronous process?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "1000";
    else
      if dir = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

hard

A. Correct implementation for the described behavior.

B. Reset value should be "0000" instead of "1000".

C. Counting direction logic is reversed; dir='1' should count down.

D. Process should use asynchronous reset instead of synchronous.

Solution

1. Step 1: Check reset behavior

   Reset sets count to "1000" as required, synchronously on rising clock edge.

2. Step 2: Verify counting direction logic

   dir='1' triggers count increment, dir='0' triggers decrement, matching the requirement.

3. Step 3: Confirm synchronous reset usage

   Reset is synchronous, which is acceptable and matches the problem statement.

4. Final Answer:

   Correct implementation for the described behavior. -> Option A

5. Quick Check:

   Synchronous reset and correct dir logic [OK]

Hint: Match reset value and dir logic exactly as specified [OK]

Common Mistakes:

• Using wrong reset value
• Reversing count up/down logic
• Confusing synchronous and asynchronous reset