Up-down counter with control in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output count after 5 clock cycles?

Consider this VHDL process for an up-down counter with control signals.

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      count <= 0;
    elsif enable = '1' then
      if up_down = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

Assuming count starts at 0, reset is '0', enable is '1', and up_down is '1', what is the value of count after 5 clock cycles?

VHDL

signal count : integer := 0;
signal clk : std_logic;
signal reset : std_logic := '0';
signal enable : std_logic := '1';
signal up_down : std_logic := '1';

A -5

B 0

C 5

D 1

💡 Hint

Count increments by 1 each clock cycle when up_down is '1' and enable is '1'.

The counter starts at 0 and increments by 1 each clock cycle because up_down is '1' and enable is '1'. After 5 cycles, the count is 5.

❓ Predict Output

intermediate

What happens if reset is asserted during counting?

Given the same process as before, what is the value of count immediately after reset is set to '1' on a rising clock edge?

VHDL

signal count : integer := 10;
signal clk : std_logic;
signal reset : std_logic := '1';
signal enable : std_logic := '1';
signal up_down : std_logic := '0';

A 1

B 10

C -1

D 0

💡 Hint

Reset sets the count to zero immediately on the rising edge.

The reset condition sets count to 0 regardless of other signals.

🔧 Debug

advanced

Identify the syntax error in this VHDL counter process

Find the syntax error in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      count <= 0
    elsif enable = '1' then
      if up_down = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

A Missing semicolon after 'count <= 0'

B Incorrect use of 'elsif' instead of 'else if'

C Missing 'begin' keyword after process declaration

D Using '=' instead of ':=' for signal assignment

💡 Hint

Check each assignment statement for proper termination.

In VHDL, each signal assignment must end with a semicolon. The line count <= 0 is missing a semicolon.

🧠 Conceptual

advanced

What is the effect of 'enable' signal in the counter process?

In the up-down counter process, what is the role of the enable signal?

A It allows the counter to increment or decrement only when 'enable' is '1'

B It resets the counter to zero when 'enable' is '1'

C It controls the clock frequency of the counter

D It determines the direction of counting

💡 Hint

Think about when the counter changes its value.

The enable signal gates the counting operation. The counter updates only if enable is '1'.

❓ Predict Output

expert

What is the final count value after this sequence of signals?

Given the following initial conditions and signal changes on rising clock edges:

• Initial count = 3
• reset = '0' throughout
• enable = '1' throughout
• up_down sequence over 6 clock cycles: '1', '1', '0', '0', '1', '0'

What is the value of count after 6 clock cycles?

VHDL

signal count : integer := 3;
signal reset : std_logic := '0';
signal enable : std_logic := '1';
signal up_down : std_logic_vector(5 downto 0) := "110010";

A 4

B 3

C 5

D 2

💡 Hint

Increment when up_down='1', decrement when '0'. Start at 3.

Counting steps: 3+1=4, 4+1=5, 5-1=4, 4-1=3, 3+1=4, 4-1=3. Final count is 3.

Recheck carefully: The last step is decrement, so final count is 3.

Correction: The sequence is 1,1,0,0,1,0

Stepwise: 3+1=4, 4+1=5, 5-1=4, 4-1=3, 3+1=4, 4-1=3

Final count is 3.

Practice

1. What does an up-down counter do in VHDL when the control signal is set to '1'?

easy

A. It counts down by decreasing the value on each clock pulse.

B. It resets the counter to zero immediately.

C. It holds the current count value without change.

D. It counts up by increasing the value on each clock pulse.

Solution

1. Step 1: Understand the control signal meaning

   In an up-down counter, the control signal '1' usually means count up.

2. Step 2: Identify the counting behavior

   When control is '1', the counter increments its value on each clock pulse.

3. Final Answer:

   It counts up by increasing the value on each clock pulse. -> Option D

4. Quick Check:

   Control '1' means count up [OK]

Hint: Control '1' means count up, '0' means count down [OK]

Common Mistakes:

• Confusing control '1' with reset signal
• Thinking control '1' holds the value
• Mixing up count up and count down signals

2. Which of the following is the correct VHDL syntax to declare a 4-bit up-down counter signal named count?

easy

A. signal count : bit_vector(4 downto 1);

B. signal count : std_logic_vector(3 downto 0);

C. signal count : integer range 0 to 15;

D. signal count : std_logic_vector(0 to 3);

Solution

1. Step 1: Identify correct type and range for 4-bit vector

   std_logic_vector(3 downto 0) is the standard way to declare a 4-bit vector from bit 3 down to 0.

2. Step 2: Check other options for errors

   signal count : integer range 0 to 15; uses integer, not vector; signal count : bit_vector(4 downto 1); uses bit_vector with wrong range; signal count : std_logic_vector(0 to 3); uses ascending range which is less common and may cause confusion.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option B

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Incorrect range direction (0 to 3 instead of 3 downto 0)
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a 3-bit up-down counter with control signal up_down and synchronous reset rst, what is the value of count after 3 clock cycles if rst = '0' and up_down = '0' initially?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "000";
    else
      if up_down = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

medium

A. "111"

B. "011"

C. "101"

D. "001"

Solution

1. Step 1: Understand initial conditions and counting direction

   Reset is '0', so no reset occurs. up_down = '0' means count down. Initial count is unknown but assumed 0 at start.

2. Step 2: Calculate count after each clock cycle

   Cycle 1: count = 0 - 1 = 7 (since 3-bit unsigned wraps around)
   Cycle 2: count = 7 - 1 = 6
   Cycle 3: count = 6 - 1 = 5 (binary "101")

3. Final Answer:

   "101" -> Option C

4. Quick Check:

   Counting down 3 times from 0 wraps to 5 [OK]

Hint: Count down wraps around 0 to max value in unsigned [OK]

Common Mistakes:

• Assuming count starts at zero without reset
• Ignoring wrap-around behavior in unsigned counters
• Mixing up count up and count down logic

4. Identify the error in this VHDL snippet for an up-down counter process:

process(clk)
begin
  if clk'event and clk = '1' then
    if rst = '1' then
      count <= (others => '0');
    elsif up_down = '1' then
      count <= count + 1;
    else
      count <= count - 1;
    end if;
  end if;
end process;

medium

A. Using clk'event and clk = '1' instead of rising_edge(clk)

B. Missing asynchronous reset handling

C. Incorrect use of (others => '0') for resetting count

D. No error; code is correct

Solution

1. Step 1: Check clock edge detection method

   Using clk'event and clk = '1' is legal but less safe and less recommended than rising_edge(clk) in modern VHDL.

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for reliable clock detection [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk)
• Confusing synchronous and asynchronous reset
• Incorrect reset assignment syntax

5. You want to design a 4-bit up-down counter in VHDL with a control signal dir where dir = '1' counts up and dir = '0' counts down. The counter should reset to "1000" on reset. Which code snippet correctly implements this behavior inside a synchronous process?

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      count <= "1000";
    else
      if dir = '1' then
        count <= count + 1;
      else
        count <= count - 1;
      end if;
    end if;
  end if;
end process;

hard

A. Correct implementation for the described behavior.

B. Reset value should be "0000" instead of "1000".

C. Counting direction logic is reversed; dir='1' should count down.

D. Process should use asynchronous reset instead of synchronous.

Solution

1. Step 1: Check reset behavior

   Reset sets count to "1000" as required, synchronously on rising clock edge.

2. Step 2: Verify counting direction logic

   dir='1' triggers count increment, dir='0' triggers decrement, matching the requirement.

3. Step 3: Confirm synchronous reset usage

   Reset is synchronous, which is acceptable and matches the problem statement.

4. Final Answer:

   Correct implementation for the described behavior. -> Option A

5. Quick Check:

   Synchronous reset and correct dir logic [OK]

Hint: Match reset value and dir logic exactly as specified [OK]

Common Mistakes:

• Using wrong reset value
• Reversing count up/down logic
• Confusing synchronous and asynchronous reset