Shift register in VHDL - Step-by-Step Execution

Concept Flow - Shift register in VHDL

Start: Load input bit

↓

Shift bits left

↓

Insert new bit at right

↓

Output shifted register

↓

Wait for next clock cycle

↩Back to Start

The shift register loads a new bit each clock cycle, shifts all bits to the left, inserts the new bit at the right, and outputs the updated register.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    reg <= reg(reg'length-2 downto 0) & data_in;
  end if;
end process;

On each clock rising edge, the register shifts left and inserts the new input bit at the right.

Execution Table

Step	clk rising_edge?	reg before	data_in	reg after	Output
1	Yes	"0000"	'1'	"000" & '1' = "001"	"001"
2	Yes	"001"	'0'	"01" & '0' = "010"	"010"
3	Yes	"010"	'1'	"10" & '1' = "101"	"101"
4	Yes	"101"	'1'	"01" & '1' = "011"	"011"
5	No	"011"	'0'	"011" (unchanged)	"011"

💡 At step 5, no rising edge detected, so register does not update.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
reg	"0000"	"001"	"010"	"101"	"011"	"011"
data_in	N/A	'1'	'0'	'1'	'1'	'0'
clk rising_edge	N/A	Yes	Yes	Yes	Yes	No

Key Moments - 2 Insights

Why does the register not change when clk rising_edge is No (step 5)?

Because the process updates the register only on the rising edge of clk, so when there is no rising edge, the register keeps its previous value as shown in execution_table row 5.

Why do we use reg(reg'length-2 downto 0) & data_in to shift?

This slices the register to remove the leftmost bit and appends the new input bit at the right, effectively shifting all bits left by one, as seen in the reg after column in execution_table.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of reg after step 3?

A "010"

B "001"

C "101"

D "011"

💡 Hint

Check the 'reg after' column in execution_table row 3.

At which step does the register first contain "011"?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at the 'reg after' column in execution_table for the value "011".

If data_in was '0' at step 2, how would reg change after step 2?

A "010"

B "000"

C "001"

D "100"

💡 Hint

Refer to execution_table and imagine data_in as '0' at step 2, shifting bits left and adding '0'.

Concept Snapshot

Shift register in VHDL:
- On rising clock edge, shift bits left.
- Insert new input bit at right.
- Syntax: reg <= reg(reg'length-2 downto 0) & data_in;
- Output updated register each cycle.
- No clock edge means no change.

Full Transcript

This visual execution shows a shift register in VHDL that updates on each rising clock edge. The register shifts all bits left by slicing off the leftmost bit and appending the new input bit at the right. The execution table traces each step with the clock edge, input bit, and register state before and after. The variable tracker shows how reg and data_in change over time. Key moments clarify why the register only updates on clock edges and how the shifting works. The quiz tests understanding of register values at specific steps and effects of input changes.

Practice

1. What is the main purpose of a shift register in VHDL?

easy

A. To perform arithmetic operations on numbers

B. To move bits step by step on each clock pulse

C. To store large amounts of data permanently

D. To generate random numbers

Solution

1. Step 1: Understand the function of a shift register

   A shift register moves bits through a series of flip-flops, shifting data on each clock pulse.

2. Step 2: Compare options with the function

   Only To move bits step by step on each clock pulse describes moving bits step by step on clock pulses, which matches the shift register's purpose.

3. Final Answer:

   To move bits step by step on each clock pulse -> Option B

4. Quick Check:

   Shift register = bit shifting [OK]

Hint: Shift register moves bits on clock edges [OK]

Common Mistakes:

• Confusing shift register with memory storage
• Thinking it performs arithmetic
• Assuming it generates random data

2. Which of the following is the correct way to declare a 4-bit shift register signal in VHDL?

easy

A. signal shift_reg : bit_vector(0 to 4);

B. signal shift_reg : integer range 0 to 3;

C. signal shift_reg : std_logic_vector(0 to 4);

D. signal shift_reg : std_logic_vector(3 downto 0);

Solution

1. Step 1: Understand VHDL signal declaration for vectors

   In VHDL, std_logic_vector is used for bit vectors, and ranges are usually declared with downto for descending indexes.

2. Step 2: Check each option

   signal shift_reg : std_logic_vector(3 downto 0); uses std_logic_vector(3 downto 0), which is correct for a 4-bit vector. signal shift_reg : integer range 0 to 3; uses integer, which is incorrect. signal shift_reg : bit_vector(0 to 4); uses bit_vector but with wrong range size (0 to 4 is 5 bits). signal shift_reg : std_logic_vector(0 to 4); uses std_logic_vector but with wrong range size (0 to 4 is 5 bits).

3. Final Answer:

   signal shift_reg : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   std_logic_vector with downto for 4 bits = signal shift_reg : std_logic_vector(3 downto 0); [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit register [OK]

Common Mistakes:

• Using integer instead of vector type
• Incorrect vector range size
• Confusing bit_vector with std_logic_vector

3. Given the following VHDL process for a 4-bit shift register, what will be the value of shift_reg after two rising clock edges if the input data_in is '1' and initial shift_reg is "0000"?

process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. "1000"

B. "1110"

C. "1100"

D. "0011"

Solution

1. Step 1: Understand the shift operation

   On each rising clock edge, the new bit data_in ('1') is shifted into the leftmost bit, and the rest of the bits shift right by one.

2. Step 2: Calculate after first clock edge

   Initial shift_reg = "0000".
   After first clock: shift_reg = '1' & "000" = "1000".

3. Step 3: Calculate after second clock edge

   Now shift_reg = "1000".
   After second clock: shift_reg = '1' & "100" = "1100".

4. Final Answer:

   "1100" -> Option C

5. Quick Check:

   Shift left with input '1' twice = "1100" [OK]

Hint: Concatenate input with shifted bits each clock [OK]

Common Mistakes:

• Not shifting bits correctly
• Confusing bit order in concatenation
• Forgetting initial value

4. Identify the error in this VHDL shift register process:

process(clk)
begin
  if clk = '1' then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. Incorrect clock edge detection

B. Missing reset signal

C. Wrong concatenation order

D. Signal assignment should use <= not :=

Solution

1. Step 1: Check clock condition

   The process uses if clk = '1' then which triggers whenever clk is high, not just on rising edge.

2. Step 2: Correct clock edge detection

   Proper edge detection in VHDL uses if rising_edge(clk) then to trigger only on the clock's rising edge.

3. Final Answer:

   Incorrect clock edge detection -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock triggers [OK]

Hint: Use rising_edge(clk) for clock events [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Confusing signal assignment operators

5. You want to design a 4-bit shift register in VHDL that shifts right on each clock and asynchronously resets to "0000". Which code snippet correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
shift_reg <= (others => '0');
elsif rising_edge(clk) then
shift_reg <= shift_reg(2 downto 0) & data_in;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
shift_reg <= (others => '0');
else
shift_reg <= data_in & shift_reg(3 downto 1);
end if;
end if;
end process;

C. process(reset, clk)
begin
if rising_edge(clk) then
if reset = '1' then
shift_reg <= (others => '0');
else
shift_reg <= shift_reg(3 downto 1) & data_in;
end if;
end if;
end process;

D. process(reset, clk)
begin
if reset = '1' then
shift_reg <= (others => '0');
elsif rising_edge(clk) then
shift_reg <= shift_reg(3 downto 1) & data_in;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   An asynchronous reset is checked first in the sensitivity list and outside the clock edge condition, so if reset = '1' then comes before elsif rising_edge(clk).

2. Step 2: Check shift direction and concatenation

   Shifting right means bits move to lower indexes, so new bit data_in is concatenated at the right end: shift_reg(2 downto 0) & data_in.

3. Step 3: Verify code snippet

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; matches asynchronous reset first, then rising edge clock shift right with correct concatenation.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; -> Option A

5. Quick Check:

   Async reset first, then shift right = process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; [OK]

Hint: Async reset checked before clock edge [OK]

Common Mistakes:

• Placing reset inside clock edge condition
• Wrong bit concatenation order for shift direction
• Missing reset in sensitivity list