Shift register in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this 4-bit shift register after 3 clock cycles?

Consider this 4-bit shift register initialized to "0000". On each rising clock edge, it shifts in the input bit '1'. What is the content of the register after 3 clock cycles?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_in : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR (3 downto 0));
end shift_reg;

architecture Behavioral of shift_reg is
    signal reg : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            reg <= reg(2 downto 0) & data_in;
        end if;
    end process;
    data_out <= reg;
end Behavioral;

A "0001"

B "1111"

C "0011"

D "0111"

💡 Hint

Each clock cycle shifts the bits left and adds the new input bit at the right end.

Initially, the register is "0000". After 1 clock cycle, it becomes "0001". After 2 cycles, "0011". After 3 cycles, "0111".

🧠 Conceptual

intermediate

Which statement best describes the behavior of this VHDL shift register?

Given a shift register that shifts bits to the left on each rising clock edge and inserts a new bit at the right, which of the following best describes its function?

A It rotates bits circularly without inserting new bits.

B It moves bits towards the least significant bit and inserts new bits at the most significant bit.

C It moves bits towards the most significant bit and inserts new bits at the least significant bit.

D It clears all bits on every clock cycle.

💡 Hint

Think about the direction bits move and where the new bit enters.

The register shifts bits left (towards MSB) and inserts the new bit at the right (LSB).

🔧 Debug

advanced

What error does this VHDL shift register code produce?

Examine this VHDL code snippet for a shift register. What error will occur when compiling?

VHDL

process(clk)
begin
    if rising_edge(clk) then
        reg <= reg(3 downto 1) & data_in;
    end if;
end process;

A Index range error: reg(3 downto 1) is invalid for a 4-bit vector.

B Syntax error: missing reset condition in process sensitivity list.

C No error, code compiles and runs correctly.

D Type mismatch error between reg and data_in.

💡 Hint

Check the vector slice range carefully.

If reg is 4 bits (3 downto 0), slicing reg(3 downto 1) gives 3 bits, but concatenating with data_in (1 bit) results in 4 bits. This is valid. However, if reg is declared differently, or if the slice is out of range, an index error occurs. The question assumes reg is 4 bits (3 downto 0), so this slice is valid. But if reg is declared as (0 to 3), this slice is invalid.

Given the code snippet alone, the most likely error is an index range error if reg is declared (0 to 3).

📝 Syntax

advanced

Which option correctly declares a 4-bit shift register signal in VHDL?

Choose the correct VHDL signal declaration for a 4-bit shift register named reg with bits indexed from 3 down to 0.

A signal reg : std_logic_vector(0 downto 3);

B signal reg : std_logic_vector(3 downto 0);

C signal reg : std_logic_vector(4 downto 1);

D signal reg : std_logic_vector(0 to 3);

💡 Hint

Remember the direction of the index range for descending order.

std_logic_vector(3 downto 0) declares a 4-bit vector with index 3 as the most significant bit and 0 as the least significant bit.

🚀 Application

expert

How many clock cycles are needed to fill a 5-bit shift register with input '1' bits starting from zero?

A 5-bit shift register is initialized to all zeros. On each rising clock edge, it shifts left and inserts a '1' at the right. How many clock cycles are required until the register contains all ones?

A 5

B 4

C 6

D 3

💡 Hint

Each clock cycle inserts one '1' bit at the right end.

Starting from "00000", after 1 cycle: "00001", after 2: "00011", after 3: "00111", after 4: "01111", after 5: "11111".

Practice

1. What is the main purpose of a shift register in VHDL?

easy

A. To perform arithmetic operations on numbers

B. To move bits step by step on each clock pulse

C. To store large amounts of data permanently

D. To generate random numbers

Solution

1. Step 1: Understand the function of a shift register

   A shift register moves bits through a series of flip-flops, shifting data on each clock pulse.

2. Step 2: Compare options with the function

   Only To move bits step by step on each clock pulse describes moving bits step by step on clock pulses, which matches the shift register's purpose.

3. Final Answer:

   To move bits step by step on each clock pulse -> Option B

4. Quick Check:

   Shift register = bit shifting [OK]

Hint: Shift register moves bits on clock edges [OK]

Common Mistakes:

• Confusing shift register with memory storage
• Thinking it performs arithmetic
• Assuming it generates random data

2. Which of the following is the correct way to declare a 4-bit shift register signal in VHDL?

easy

A. signal shift_reg : bit_vector(0 to 4);

B. signal shift_reg : integer range 0 to 3;

C. signal shift_reg : std_logic_vector(0 to 4);

D. signal shift_reg : std_logic_vector(3 downto 0);

Solution

1. Step 1: Understand VHDL signal declaration for vectors

   In VHDL, std_logic_vector is used for bit vectors, and ranges are usually declared with downto for descending indexes.

2. Step 2: Check each option

   signal shift_reg : std_logic_vector(3 downto 0); uses std_logic_vector(3 downto 0), which is correct for a 4-bit vector. signal shift_reg : integer range 0 to 3; uses integer, which is incorrect. signal shift_reg : bit_vector(0 to 4); uses bit_vector but with wrong range size (0 to 4 is 5 bits). signal shift_reg : std_logic_vector(0 to 4); uses std_logic_vector but with wrong range size (0 to 4 is 5 bits).

3. Final Answer:

   signal shift_reg : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   std_logic_vector with downto for 4 bits = signal shift_reg : std_logic_vector(3 downto 0); [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit register [OK]

Common Mistakes:

• Using integer instead of vector type
• Incorrect vector range size
• Confusing bit_vector with std_logic_vector

3. Given the following VHDL process for a 4-bit shift register, what will be the value of shift_reg after two rising clock edges if the input data_in is '1' and initial shift_reg is "0000"?

process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. "1000"

B. "1110"

C. "1100"

D. "0011"

Solution

1. Step 1: Understand the shift operation

   On each rising clock edge, the new bit data_in ('1') is shifted into the leftmost bit, and the rest of the bits shift right by one.

2. Step 2: Calculate after first clock edge

   Initial shift_reg = "0000".
   After first clock: shift_reg = '1' & "000" = "1000".

3. Step 3: Calculate after second clock edge

   Now shift_reg = "1000".
   After second clock: shift_reg = '1' & "100" = "1100".

4. Final Answer:

   "1100" -> Option C

5. Quick Check:

   Shift left with input '1' twice = "1100" [OK]

Hint: Concatenate input with shifted bits each clock [OK]

Common Mistakes:

• Not shifting bits correctly
• Confusing bit order in concatenation
• Forgetting initial value

4. Identify the error in this VHDL shift register process:

process(clk)
begin
  if clk = '1' then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. Incorrect clock edge detection

B. Missing reset signal

C. Wrong concatenation order

D. Signal assignment should use <= not :=

Solution

1. Step 1: Check clock condition

   The process uses if clk = '1' then which triggers whenever clk is high, not just on rising edge.

2. Step 2: Correct clock edge detection

   Proper edge detection in VHDL uses if rising_edge(clk) then to trigger only on the clock's rising edge.

3. Final Answer:

   Incorrect clock edge detection -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock triggers [OK]

Hint: Use rising_edge(clk) for clock events [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Confusing signal assignment operators

5. You want to design a 4-bit shift register in VHDL that shifts right on each clock and asynchronously resets to "0000". Which code snippet correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
shift_reg <= (others => '0');
elsif rising_edge(clk) then
shift_reg <= shift_reg(2 downto 0) & data_in;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
shift_reg <= (others => '0');
else
shift_reg <= data_in & shift_reg(3 downto 1);
end if;
end if;
end process;

C. process(reset, clk)
begin
if rising_edge(clk) then
if reset = '1' then
shift_reg <= (others => '0');
else
shift_reg <= shift_reg(3 downto 1) & data_in;
end if;
end if;
end process;

D. process(reset, clk)
begin
if reset = '1' then
shift_reg <= (others => '0');
elsif rising_edge(clk) then
shift_reg <= shift_reg(3 downto 1) & data_in;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   An asynchronous reset is checked first in the sensitivity list and outside the clock edge condition, so if reset = '1' then comes before elsif rising_edge(clk).

2. Step 2: Check shift direction and concatenation

   Shifting right means bits move to lower indexes, so new bit data_in is concatenated at the right end: shift_reg(2 downto 0) & data_in.

3. Step 3: Verify code snippet

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; matches asynchronous reset first, then rising edge clock shift right with correct concatenation.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; -> Option A

5. Quick Check:

   Async reset first, then shift right = process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; [OK]

Hint: Async reset checked before clock edge [OK]

Common Mistakes:

• Placing reset inside clock edge condition
• Wrong bit concatenation order for shift direction
• Missing reset in sensitivity list