Shift register in VHDL - Mini Project: Build & Apply

Shift Register in VHDL

📖 Scenario: You are designing a simple digital circuit that moves bits through a series of flip-flops, called a shift register. This is useful in many electronics applications like data storage, communication, and timing.

🎯 Goal: Build a 4-bit shift register in VHDL that shifts bits to the right on each clock pulse.

📋 What You'll Learn

Create a 4-bit std_logic_vector signal to hold the register state

Add a clock input signal

Implement the shift operation on the rising edge of the clock

Output the current state of the shift register

💡 Why This Matters

🌍 Real World

Shift registers are used in digital electronics for data storage, data transfer, and timing control in devices like communication systems and microcontrollers.

💼 Career

Understanding shift registers is essential for hardware engineers and FPGA developers working on digital circuit design and embedded systems.

1

Create the shift register signal

Create a signal called shift_reg of type std_logic_vector(3 downto 0) and initialize it to "0000".

VHDL

-- Your code here

Hint

Use signal keyword and initialize with 4 zeros in quotes.

2

Add the clock input

Declare an input signal called clk of type std_logic to represent the clock.

VHDL

signal shift_reg : std_logic_vector(3 downto 0) := "0000";
-- Your code here

Hint

Use signal clk : std_logic; to declare the clock.

3

Implement the shift logic

Write a process sensitive to clk that on the rising edge of clk shifts shift_reg right by one bit, inserting '0' at the leftmost bit.

VHDL

signal shift_reg : std_logic_vector(3 downto 0) := "0000";
signal clk : std_logic;

-- Your code here

Hint

Use process(clk) and if rising_edge(clk) then to detect clock edges. Shift by concatenating '0' with the upper bits.

4

Output the shift register state

Write a statement to output the current value of shift_reg using report to display it as a string.

VHDL

signal shift_reg : std_logic_vector(3 downto 0) := "0000";
signal clk : std_logic;

process(clk) is
begin
    if rising_edge(clk) then
        shift_reg <= '0' & shift_reg(3 downto 1);
    end if;
end process;

-- Your code here

Hint

Use report "Shift Register state: " & shift_reg; inside the clock process.

Practice

1. What is the main purpose of a shift register in VHDL?

easy

A. To perform arithmetic operations on numbers

B. To move bits step by step on each clock pulse

C. To store large amounts of data permanently

D. To generate random numbers

Solution

1. Step 1: Understand the function of a shift register

   A shift register moves bits through a series of flip-flops, shifting data on each clock pulse.

2. Step 2: Compare options with the function

   Only To move bits step by step on each clock pulse describes moving bits step by step on clock pulses, which matches the shift register's purpose.

3. Final Answer:

   To move bits step by step on each clock pulse -> Option B

4. Quick Check:

   Shift register = bit shifting [OK]

Hint: Shift register moves bits on clock edges [OK]

Common Mistakes:

• Confusing shift register with memory storage
• Thinking it performs arithmetic
• Assuming it generates random data

2. Which of the following is the correct way to declare a 4-bit shift register signal in VHDL?

easy

A. signal shift_reg : bit_vector(0 to 4);

B. signal shift_reg : integer range 0 to 3;

C. signal shift_reg : std_logic_vector(0 to 4);

D. signal shift_reg : std_logic_vector(3 downto 0);

Solution

1. Step 1: Understand VHDL signal declaration for vectors

   In VHDL, std_logic_vector is used for bit vectors, and ranges are usually declared with downto for descending indexes.

2. Step 2: Check each option

   signal shift_reg : std_logic_vector(3 downto 0); uses std_logic_vector(3 downto 0), which is correct for a 4-bit vector. signal shift_reg : integer range 0 to 3; uses integer, which is incorrect. signal shift_reg : bit_vector(0 to 4); uses bit_vector but with wrong range size (0 to 4 is 5 bits). signal shift_reg : std_logic_vector(0 to 4); uses std_logic_vector but with wrong range size (0 to 4 is 5 bits).

3. Final Answer:

   signal shift_reg : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   std_logic_vector with downto for 4 bits = signal shift_reg : std_logic_vector(3 downto 0); [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit register [OK]

Common Mistakes:

• Using integer instead of vector type
• Incorrect vector range size
• Confusing bit_vector with std_logic_vector

3. Given the following VHDL process for a 4-bit shift register, what will be the value of shift_reg after two rising clock edges if the input data_in is '1' and initial shift_reg is "0000"?

process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. "1000"

B. "1110"

C. "1100"

D. "0011"

Solution

1. Step 1: Understand the shift operation

   On each rising clock edge, the new bit data_in ('1') is shifted into the leftmost bit, and the rest of the bits shift right by one.

2. Step 2: Calculate after first clock edge

   Initial shift_reg = "0000".
After first clock: shift_reg = '1' & "000" = "1000".

3. Step 3: Calculate after second clock edge

   Now shift_reg = "1000".
After second clock: shift_reg = '1' & "100" = "1100".

4. Final Answer:

   "1100" -> Option C

5. Quick Check:

   Shift left with input '1' twice = "1100" [OK]

Hint: Concatenate input with shifted bits each clock [OK]

Common Mistakes:

• Not shifting bits correctly
• Confusing bit order in concatenation
• Forgetting initial value

4. Identify the error in this VHDL shift register process:

process(clk)
begin
  if clk = '1' then
    shift_reg <= data_in & shift_reg(3 downto 1);
  end if;
end process;

medium

A. Incorrect clock edge detection

B. Missing reset signal

C. Wrong concatenation order

D. Signal assignment should use <= not :=

Solution

1. Step 1: Check clock condition

   The process uses if clk = '1' then which triggers whenever clk is high, not just on rising edge.

2. Step 2: Correct clock edge detection

   Proper edge detection in VHDL uses if rising_edge(clk) then to trigger only on the clock's rising edge.

3. Final Answer:

   Incorrect clock edge detection -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock triggers [OK]

Hint: Use rising_edge(clk) for clock events [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Confusing signal assignment operators

5. You want to design a 4-bit shift register in VHDL that shifts right on each clock and asynchronously resets to "0000". Which code snippet correctly implements this behavior?

hard

A. process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then shift_reg <= (others => '0'); else shift_reg <= data_in & shift_reg(3 downto 1); end if; end if; end process;

C. process(reset, clk) begin if rising_edge(clk) then if reset = '1' then shift_reg <= (others => '0'); else shift_reg <= shift_reg(3 downto 1) & data_in; end if; end if; end process;

D. process(reset, clk) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(3 downto 1) & data_in; end if; end process;

Solution

1. Step 1: Identify asynchronous reset

   An asynchronous reset is checked first in the sensitivity list and outside the clock edge condition, so if reset = '1' then comes before elsif rising_edge(clk).

2. Step 2: Check shift direction and concatenation

   Shifting right means bits move to lower indexes, so new bit data_in is concatenated at the right end: shift_reg(2 downto 0) & data_in.

3. Step 3: Verify code snippet

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; matches asynchronous reset first, then rising edge clock shift right with correct concatenation.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; -> Option A

5. Quick Check:

   Async reset first, then shift right = process(clk, reset) begin if reset = '1' then shift_reg <= (others => '0'); elsif rising_edge(clk) then shift_reg <= shift_reg(2 downto 0) & data_in; end if; end process; [OK]

Hint: Async reset checked before clock edge [OK]

Common Mistakes:

• Placing reset inside clock edge condition
• Wrong bit concatenation order for shift direction
• Missing reset in sensitivity list