Binary up counter in VHDL - Step-by-Step Execution

Concept Flow - Binary up counter

Reset counter to 0

↓

Wait for clock rising edge

↓

Increment counter by 1

↓

Check if counter reached max

↓

Output counter

The binary up counter resets to zero, then on each clock rising edge increments by one until it reaches its max value, then resets again.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(clk) then
    if count = "1111" then
      count <= (others => '0');
    else
      count <= count + 1;
    end if;
  end if;
end process;

This VHDL process resets the counter to zero on reset, otherwise increments it by 1 on each clock rising edge, and resets to zero when max value is reached.

Execution Table

Step	reset	clk	rising_edge(clk)?	count before	Action	count after	Output
1	1	X	No	0000	Reset active	0000	0000
2	0	0->1	Yes	0000	Increment	0001	0001
3	0	0->1	Yes	0001	Increment	0010	0010
4	0	0->1	Yes	0010	Increment	0011	0011
5	0	0->1	Yes	0011	Increment	0100	0100
6	0	0->1	Yes	0100	Increment	0101	0101
7	0	0->1	Yes	0101	Increment	0110	0110
8	0	0->1	Yes	0110	Increment	0111	0111
9	0	0->1	Yes	0111	Increment	1000	1000
10	0	0->1	Yes	1000	Increment	1001	1001
11	0	0->1	Yes	1001	Increment	1010	1010
12	0	0->1	Yes	1010	Increment	1011	1011
13	0	0->1	Yes	1011	Increment	1100	1100
14	0	0->1	Yes	1100	Increment	1101	1101
15	0	0->1	Yes	1101	Increment	1110	1110
16	0	0->1	Yes	1110	Increment	1111	1111
17	0	0->1	Yes	1111	Increment with overflow	0000	0000
18	1	X	No	0000	Reset active	0000	0000

💡 Counter resets after reaching max value 1111 (15 decimal), then continues counting again.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	After 12	After 13	After 14	After 15	After 16	After 17	Final
count	0000	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111	0000	0000

Key Moments - 3 Insights

Why does the counter reset to 0000 after reaching 1111?

Because the counter is limited to 4 bits, adding 1 to 1111 causes an overflow back to 0000, as shown in execution_table row 17.

What happens if reset is active during counting?

When reset = '1', the counter immediately sets to 0000 regardless of clock, as shown in rows 1 and 18 of the execution_table.

Why do we only increment on rising edge of clk?

The process checks rising_edge(clk) to ensure count increments only once per clock cycle, preventing multiple increments within the same clock period (see execution_table column 'rising_edge(clk)?').

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after step 5?

A 0011

B 0101

C 0100

D 0010

💡 Hint

Check the 'count after' column at row 5 in the execution_table.

At which step does the counter overflow and reset to 0000?

A Step 17

B Step 18

C Step 16

D Step 15

💡 Hint

Look for 'Increment with overflow' action in the execution_table.

If reset is set to '1' at step 10, what will be the count value after that step?

A 1001

B 0000

C 1010

D 1111

💡 Hint

Refer to execution_table rows 1 and 18 where reset = '1' causes count to reset to 0000.

Concept Snapshot

Binary up counter in VHDL:
- Uses process sensitive to clk and reset
- On reset='1', count set to 0
- On rising_edge(clk), count increments by 1
- Count wraps around after max value (e.g., 1111 for 4 bits)
- Output is current count value
- Commonly used for timing and sequencing

Full Transcript

This visual execution shows a 4-bit binary up counter in VHDL. The counter resets to zero when reset is active. On each rising edge of the clock, the counter increments by one. When the counter reaches its maximum value 1111 (decimal 15), it overflows and resets back to 0000. The execution table traces each step, showing the reset signal, clock edge detection, count before and after increment, and the output. The variable tracker follows the count value through each clock cycle. Key moments clarify why the counter resets on overflow, the effect of reset, and why increments happen only on clock rising edges. The quiz tests understanding of count values at specific steps and the effect of reset. This is a fundamental digital design pattern for counting events or time intervals.

Practice

1. What does a binary up counter do in VHDL?

easy

A. It increases the count by one on each clock pulse.

B. It decreases the count by one on each clock pulse.

C. It resets the count to a random value on each clock pulse.

D. It holds the count constant regardless of clock pulses.

Solution

1. Step 1: Understand the function of a binary up counter

   A binary up counter increments its value by one every time it detects a clock pulse.

2. Step 2: Compare options with the definition

   "It increases the count by one on each clock pulse." correctly describes this behavior.

3. Final Answer:

   It increases the count by one on each clock pulse. -> Option A

4. Quick Check:

   Binary up counter = increments count [OK]

Hint: Remember: up counter counts up by 1 each clock pulse [OK]

Common Mistakes:

• Confusing up counter with down counter
• Thinking it resets automatically without reset signal
• Assuming it counts randomly

2. What is the preferred VHDL syntax to detect a rising clock edge in a binary up counter?

easy

A. if clock'event and clock = '1' then

B. if clock = '1' then

C. if rising_edge(clock) then

D. if clock'last_value = '0' then

Solution

1. Step 1: Identify the standard way to detect rising edge in VHDL

   The recommended and modern way is to use the function rising_edge(clock) which returns true on the clock's rising edge.

2. Step 2: Check each option

   if rising_edge(clock) then uses rising_edge(clock), which is correct. if clock'event and clock = '1' then is older style but less preferred. Options C and D are incorrect for detecting edges.

3. Final Answer:

   if rising_edge(clock) then -> Option C

4. Quick Check:

   Use rising_edge(clock) for clock edge detection [OK]

Hint: Use rising_edge(clock) for clean clock detection [OK]

Common Mistakes:

• Using clock = '1' without edge detection
• Confusing clock'event with rising_edge
• Using non-existent attributes like clock'last_value

3. Given this VHDL process for a 3-bit binary up counter, what is the value of count after 4 rising clock edges if reset is '0'?

process(clock, reset)
begin
  if reset = '1' then
    count <= "000";
  elsif rising_edge(clock) then
    count <= count + 1;
  end if;
end process;

medium

A. "010"

B. "011"

C. "101"

D. "100"

Solution

1. Step 1: Determine initial condition

   Reset is '0' (inactive), so no reset occurs during the clock edges. Assume initial count is "000" (standard for such simulation problems).

2. Step 2: Trace increments after 4 rising clock edges

   Start: "000" (0) -> 1st: "001" (1) -> 2nd: "010" (2) -> 3rd: "011" (3) -> 4th: "100" (4).

3. Final Answer:

   "100" -> Option D

4. Quick Check:

   4 increments from 0 = "100" [OK]

Hint: Count increments by 1 each clock; convert decimal to binary [OK]

Common Mistakes:

• Confusing reset active level
• Miscounting increments
• Mixing binary values

4. Identify the error in this VHDL binary up counter process:

process(clock, reset)
begin
  if rising_edge(clock) then
    if reset = '1' then
      count <= "000";
    else
      count <= count + 1;
    end if;
end process;

medium

A. The process sensitivity list is incorrect.

B. Reset check should be outside the rising_edge(clock) condition.

C. Missing semicolon after count <= count + 1.

D. The count signal is not declared as a std_logic_vector.

Solution

1. Step 1: Analyze reset placement in process

   Reset is asynchronous and should be checked outside the rising_edge(clock) condition to reset immediately when active.

2. Step 2: Confirm correct reset handling

   In the code, reset is checked inside rising_edge(clock), making it synchronous reset. If asynchronous reset is intended, reset check must be outside rising_edge(clock).

3. Final Answer:

   Reset check should be outside the rising_edge(clock) condition. -> Option B

4. Quick Check:

   Asynchronous reset outside clock edge [OK]

Hint: Place asynchronous reset outside rising_edge(clock) [OK]

Common Mistakes:

• Putting asynchronous reset inside clock edge
• Ignoring sensitivity list for reset
• Assuming synchronous reset without stating

5. How would you modify a 4-bit binary up counter in VHDL to reset to "1010" instead of "0000" when reset is active?

medium

A. Change the reset assignment to count <= "1010"; inside the reset condition.

B. Initialize count signal to "1010" outside the process.

C. Add count <= "1010"; inside the rising_edge(clock) condition.

D. Use count <= count + "1010"; to add reset value.

Solution

1. Step 1: Locate reset assignment in the process

   The reset condition sets count to a value when reset is active. To change reset value, modify this assignment.

2. Step 2: Assign new reset value "1010" inside reset condition

   Replace count <= "0000"; with count <= "1010"; inside the reset if statement.

3. Final Answer:

   Change the reset assignment to count <= "1010"; inside the reset condition. -> Option A

4. Quick Check:

   Reset value set inside reset condition [OK]

Hint: Set desired reset value inside reset condition [OK]

Common Mistakes:

• Changing initial value instead of reset assignment
• Adding reset value inside clock edge
• Trying to add binary strings instead of assign