Binary up counter in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this 2-bit binary up counter after 5 clock cycles?

Consider this VHDL process for a 2-bit binary up counter with asynchronous reset:

process(clk, reset)
begin
  if reset = '1' then
    count <= "00";
  elsif rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

If the reset is deasserted at the start and the clock ticks 5 times, what is the value of count?

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(1 downto 0)
  );
end entity;

architecture rtl of counter is
  signal count_reg : unsigned(1 downto 0) := (others => '0');
begin
  process(clk, reset)
  begin
    if reset = '1' then
      count_reg <= (others => '0');
    elsif rising_edge(clk) then
      count_reg <= count_reg + 1;
    end if;
  end process;
  count <= std_logic_vector(count_reg);
end architecture;

A "010"

B "101"

C "01"

D "11"

💡 Hint

Count starts at 0 and increments by 1 each clock cycle. Remember it is 2 bits wide.

The 2-bit counter counts from 00, 01, 10, 11, then wraps around to 00, 01. After 5 clock cycles starting from 00, the count is 01 (decimal 1).

❓ Predict Output

intermediate

What is the value of a 3-bit binary up counter after 8 clock cycles?

Given a 3-bit binary up counter that increments on every rising clock edge and resets asynchronously to zero, what will be the value of the counter after 8 clock cycles?

VHDL

signal count : unsigned(2 downto 0) := (others => '0');
process(clk, reset)
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

A "001"

B "000"

C "1000"

D "111"

💡 Hint

Think about the maximum count for 3 bits and what happens after 8 increments.

A 3-bit counter counts from 0 to 7 ("000" to "111"). After 8 increments, it wraps back to "000".

🔧 Debug

advanced

What error does this VHDL binary up counter code produce?

Examine this VHDL code snippet for a 4-bit binary up counter:

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  elsif reset = '1' then
    count <= (others => '0');
  end if;
end process;

What error will this code cause during synthesis or simulation?

VHDL

signal count : unsigned(3 downto 0) := (others => '0');

A Logical error: reset condition never triggers

B Runtime error: count overflow

C Syntax error: missing reset in sensitivity list

D No error, code works correctly

💡 Hint

Check the order of conditions and sensitivity list.

The reset condition is checked after the clock edge condition, so reset will never trigger properly. Also, reset is not in the sensitivity list, so asynchronous reset won't work.

📝 Syntax

advanced

Which option correctly declares a 5-bit binary up counter signal in VHDL?

Choose the correct VHDL signal declaration for a 5-bit binary up counter using unsigned type.

A signal count : unsigned(5 downto 1) := (others => '0');

B signal count : unsigned(0 to 4) := (others => '0');

C signal count : unsigned(5 downto 0) := (others => '0');

D signal count : unsigned(4 downto 0) := (others => '0');

💡 Hint

Remember that the range defines the bit width and direction.

Unsigned vectors are usually declared with the most significant bit on the left. For 5 bits, indices 4 downto 0 give 5 bits.

🚀 Application

expert

How many unique states does a 6-bit binary up counter cycle through before repeating?

A 6-bit binary up counter increments by 1 on each clock cycle and wraps around after reaching its maximum value. How many unique states does it have before it repeats?

A 64

B 32

C 63

D 128

💡 Hint

Think about how many values can be represented with 6 bits.

A 6-bit counter can represent 2^6 = 64 unique states, from 0 to 63.

Practice

1. What does a binary up counter do in VHDL?

easy

A. It increases the count by one on each clock pulse.

B. It decreases the count by one on each clock pulse.

C. It resets the count to a random value on each clock pulse.

D. It holds the count constant regardless of clock pulses.

Solution

1. Step 1: Understand the function of a binary up counter

   A binary up counter increments its value by one every time it detects a clock pulse.

2. Step 2: Compare options with the definition

   "It increases the count by one on each clock pulse." correctly describes this behavior.

3. Final Answer:

   It increases the count by one on each clock pulse. -> Option A

4. Quick Check:

   Binary up counter = increments count [OK]

Hint: Remember: up counter counts up by 1 each clock pulse [OK]

Common Mistakes:

• Confusing up counter with down counter
• Thinking it resets automatically without reset signal
• Assuming it counts randomly

2. What is the preferred VHDL syntax to detect a rising clock edge in a binary up counter?

easy

A. if clock'event and clock = '1' then

B. if clock = '1' then

C. if rising_edge(clock) then

D. if clock'last_value = '0' then

Solution

1. Step 1: Identify the standard way to detect rising edge in VHDL

   The recommended and modern way is to use the function rising_edge(clock) which returns true on the clock's rising edge.

2. Step 2: Check each option

   if rising_edge(clock) then uses rising_edge(clock), which is correct. if clock'event and clock = '1' then is older style but less preferred. Options C and D are incorrect for detecting edges.

3. Final Answer:

   if rising_edge(clock) then -> Option C

4. Quick Check:

   Use rising_edge(clock) for clock edge detection [OK]

Hint: Use rising_edge(clock) for clean clock detection [OK]

Common Mistakes:

• Using clock = '1' without edge detection
• Confusing clock'event with rising_edge
• Using non-existent attributes like clock'last_value

3. Given this VHDL process for a 3-bit binary up counter, what is the value of count after 4 rising clock edges if reset is '0'?

process(clock, reset)
begin
  if reset = '1' then
    count <= "000";
  elsif rising_edge(clock) then
    count <= count + 1;
  end if;
end process;

medium

A. "010"

B. "011"

C. "101"

D. "100"

Solution

1. Step 1: Determine initial condition

   Reset is '0' (inactive), so no reset occurs during the clock edges. Assume initial count is "000" (standard for such simulation problems).

2. Step 2: Trace increments after 4 rising clock edges

   Start: "000" (0) -> 1st: "001" (1) -> 2nd: "010" (2) -> 3rd: "011" (3) -> 4th: "100" (4).

3. Final Answer:

   "100" -> Option D

4. Quick Check:

   4 increments from 0 = "100" [OK]

Hint: Count increments by 1 each clock; convert decimal to binary [OK]

Common Mistakes:

• Confusing reset active level
• Miscounting increments
• Mixing binary values

4. Identify the error in this VHDL binary up counter process:

process(clock, reset)
begin
  if rising_edge(clock) then
    if reset = '1' then
      count <= "000";
    else
      count <= count + 1;
    end if;
end process;

medium

A. The process sensitivity list is incorrect.

B. Reset check should be outside the rising_edge(clock) condition.

C. Missing semicolon after count <= count + 1.

D. The count signal is not declared as a std_logic_vector.

Solution

1. Step 1: Analyze reset placement in process

   Reset is asynchronous and should be checked outside the rising_edge(clock) condition to reset immediately when active.

2. Step 2: Confirm correct reset handling

   In the code, reset is checked inside rising_edge(clock), making it synchronous reset. If asynchronous reset is intended, reset check must be outside rising_edge(clock).

3. Final Answer:

   Reset check should be outside the rising_edge(clock) condition. -> Option B

4. Quick Check:

   Asynchronous reset outside clock edge [OK]

Hint: Place asynchronous reset outside rising_edge(clock) [OK]

Common Mistakes:

• Putting asynchronous reset inside clock edge
• Ignoring sensitivity list for reset
• Assuming synchronous reset without stating

5. How would you modify a 4-bit binary up counter in VHDL to reset to "1010" instead of "0000" when reset is active?

medium

A. Change the reset assignment to count <= "1010"; inside the reset condition.

B. Initialize count signal to "1010" outside the process.

C. Add count <= "1010"; inside the rising_edge(clock) condition.

D. Use count <= count + "1010"; to add reset value.

Solution

1. Step 1: Locate reset assignment in the process

   The reset condition sets count to a value when reset is active. To change reset value, modify this assignment.

2. Step 2: Assign new reset value "1010" inside reset condition

   Replace count <= "0000"; with count <= "1010"; inside the reset if statement.

3. Final Answer:

   Change the reset assignment to count <= "1010"; inside the reset condition. -> Option A

4. Quick Check:

   Reset value set inside reset condition [OK]

Hint: Set desired reset value inside reset condition [OK]

Common Mistakes:

• Changing initial value instead of reset assignment
• Adding reset value inside clock edge
• Trying to add binary strings instead of assign