Binary up counter in VHDL - Mini Project: Build & Apply

Binary up counter

📖 Scenario: You are designing a simple digital circuit that counts up in binary every clock cycle. This is a common task in electronics and digital systems.

🎯 Goal: Build a binary up counter in VHDL that increases its value by 1 on each rising edge of the clock signal.

📋 What You'll Learn

Create a 4-bit signal to hold the counter value

Use a clock signal to trigger counting

Increment the counter on each rising clock edge

Reset the counter to zero when a reset signal is active

💡 Why This Matters

🌍 Real World

Binary counters are used in digital clocks, timers, frequency dividers, and many other electronic devices to keep track of events or time.

💼 Career

Understanding counters is essential for hardware design engineers and anyone working with digital logic circuits or FPGA programming.

1

Create the counter signal

Create a 4-bit signal called counter initialized to "0000" inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity binary_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out STD_LOGIC_VECTOR (3 downto 0));
end binary_counter;

architecture Behavioral of binary_counter is
    signal counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";  -- Your code here
begin

end Behavioral;

Hint

Signals are declared inside the architecture but before the begin keyword.

2

Add process with clock and reset

Add a process named count_process that is sensitive to clk and reset. Inside it, check if reset is '1' to set counter to "0000".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity binary_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out STD_LOGIC_VECTOR (3 downto 0));
end binary_counter;

architecture Behavioral of binary_counter is
    signal counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    count_process : process(clk, reset)
    begin
        if reset = '1' then
            counter <= "0000";  -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use a process block with sensitivity list including clk and reset. Reset has priority.

3

Increment counter on rising clock edge

Inside the count_process, add an elsif condition to check for rising edge of clk using rising_edge(clk). Increment counter by 1 as an unsigned number.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binary_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out STD_LOGIC_VECTOR (3 downto 0));
end binary_counter;

architecture Behavioral of binary_counter is
    signal counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    count_process : process(clk, reset)
    begin
        if reset = '1' then
            counter <= "0000";
        elsif rising_edge(clk) then
            counter <= std_logic_vector(unsigned(counter) + 1);  -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use unsigned conversion to add 1 to the counter signal and convert back to std_logic_vector.

4

Assign counter to output

Assign the counter signal to the output port count_out using a concurrent signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binary_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out STD_LOGIC_VECTOR (3 downto 0));
end binary_counter;

architecture Behavioral of binary_counter is
    signal counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    count_process : process(clk, reset)
    begin
        if reset = '1' then
            counter <= "0000";
        elsif rising_edge(clk) then
            counter <= std_logic_vector(unsigned(counter) + 1);
        end if;
    end process;

    count_out <= counter;  -- Your code here
end Behavioral;

Hint

Use a simple concurrent assignment to connect the internal counter signal to the output port.

Practice

1. What does a binary up counter do in VHDL?

easy

A. It increases the count by one on each clock pulse.

B. It decreases the count by one on each clock pulse.

C. It resets the count to a random value on each clock pulse.

D. It holds the count constant regardless of clock pulses.

Solution

1. Step 1: Understand the function of a binary up counter

   A binary up counter increments its value by one every time it detects a clock pulse.

2. Step 2: Compare options with the definition

   "It increases the count by one on each clock pulse." correctly describes this behavior.

3. Final Answer:

   It increases the count by one on each clock pulse. -> Option A

4. Quick Check:

   Binary up counter = increments count [OK]

Hint: Remember: up counter counts up by 1 each clock pulse [OK]

Common Mistakes:

• Confusing up counter with down counter
• Thinking it resets automatically without reset signal
• Assuming it counts randomly

2. What is the preferred VHDL syntax to detect a rising clock edge in a binary up counter?

easy

A. if clock'event and clock = '1' then

B. if clock = '1' then

C. if rising_edge(clock) then

D. if clock'last_value = '0' then

Solution

1. Step 1: Identify the standard way to detect rising edge in VHDL

   The recommended and modern way is to use the function rising_edge(clock) which returns true on the clock's rising edge.

2. Step 2: Check each option

   if rising_edge(clock) then uses rising_edge(clock), which is correct. if clock'event and clock = '1' then is older style but less preferred. Options C and D are incorrect for detecting edges.

3. Final Answer:

   if rising_edge(clock) then -> Option C

4. Quick Check:

   Use rising_edge(clock) for clock edge detection [OK]

Hint: Use rising_edge(clock) for clean clock detection [OK]

Common Mistakes:

• Using clock = '1' without edge detection
• Confusing clock'event with rising_edge
• Using non-existent attributes like clock'last_value

3. Given this VHDL process for a 3-bit binary up counter, what is the value of count after 4 rising clock edges if reset is '0'?

process(clock, reset)
begin
  if reset = '1' then
    count <= "000";
  elsif rising_edge(clock) then
    count <= count + 1;
  end if;
end process;

medium

A. "010"

B. "011"

C. "101"

D. "100"

Solution

1. Step 1: Determine initial condition

   Reset is '0' (inactive), so no reset occurs during the clock edges. Assume initial count is "000" (standard for such simulation problems).

2. Step 2: Trace increments after 4 rising clock edges

   Start: "000" (0) -> 1st: "001" (1) -> 2nd: "010" (2) -> 3rd: "011" (3) -> 4th: "100" (4).

3. Final Answer:

   "100" -> Option D

4. Quick Check:

   4 increments from 0 = "100" [OK]

Hint: Count increments by 1 each clock; convert decimal to binary [OK]

Common Mistakes:

• Confusing reset active level
• Miscounting increments
• Mixing binary values

4. Identify the error in this VHDL binary up counter process:

process(clock, reset)
begin
  if rising_edge(clock) then
    if reset = '1' then
      count <= "000";
    else
      count <= count + 1;
    end if;
end process;

medium

A. The process sensitivity list is incorrect.

B. Reset check should be outside the rising_edge(clock) condition.

C. Missing semicolon after count <= count + 1.

D. The count signal is not declared as a std_logic_vector.

Solution

1. Step 1: Analyze reset placement in process

   Reset is asynchronous and should be checked outside the rising_edge(clock) condition to reset immediately when active.

2. Step 2: Confirm correct reset handling

   In the code, reset is checked inside rising_edge(clock), making it synchronous reset. If asynchronous reset is intended, reset check must be outside rising_edge(clock).

3. Final Answer:

   Reset check should be outside the rising_edge(clock) condition. -> Option B

4. Quick Check:

   Asynchronous reset outside clock edge [OK]

Hint: Place asynchronous reset outside rising_edge(clock) [OK]

Common Mistakes:

• Putting asynchronous reset inside clock edge
• Ignoring sensitivity list for reset
• Assuming synchronous reset without stating

5. How would you modify a 4-bit binary up counter in VHDL to reset to "1010" instead of "0000" when reset is active?

medium

A. Change the reset assignment to count <= "1010"; inside the reset condition.

B. Initialize count signal to "1010" outside the process.

C. Add count <= "1010"; inside the rising_edge(clock) condition.

D. Use count <= count + "1010"; to add reset value.

Solution

1. Step 1: Locate reset assignment in the process

   The reset condition sets count to a value when reset is active. To change reset value, modify this assignment.

2. Step 2: Assign new reset value "1010" inside reset condition

   Replace count <= "0000"; with count <= "1010"; inside the reset if statement.

3. Final Answer:

   Change the reset assignment to count <= "1010"; inside the reset condition. -> Option A

4. Quick Check:

   Reset value set inside reset condition [OK]

Hint: Set desired reset value inside reset condition [OK]

Common Mistakes:

• Changing initial value instead of reset assignment
• Adding reset value inside clock edge
• Trying to add binary strings instead of assign