Binary down counter in VHDL - Step-by-Step Execution

Concept Flow - Binary down counter

Start: Load max value

↓

Wait for clock edge

↓

Check if counter > 0?

No→Reset to max value

Yes↓

Decrement counter by 1

↓

Output current counter value

↓

Repeat on next clock edge

The binary down counter starts at a max value, waits for each clock tick, then decreases by one until zero, then resets.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if counter = 0 then
      counter <= max_value;
    else
      counter <= counter - 1;
    end if;
  end if;
end process;

This VHDL process counts down the counter on each clock rising edge, resetting to max_value when it reaches zero.

Execution Table

Step	clk rising_edge?	counter before	Condition (counter=0)	Action	counter after	Output
1	Yes	7	No	Decrement counter	6	6
2	Yes	6	No	Decrement counter	5	5
3	Yes	5	No	Decrement counter	4	4
4	Yes	4	No	Decrement counter	3	3
5	Yes	3	No	Decrement counter	2	2
6	Yes	2	No	Decrement counter	1	1
7	Yes	1	No	Decrement counter	0	0
8	Yes	0	Yes	Reset to max_value (7)	7	7
9	Yes	7	No	Decrement counter	6	6
Exit	No	-	-	-	-	Stop (no clock edge)

💡 Execution stops when no clock rising edge occurs.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9
counter	7	6	5	4	3	2	1	0	7	6

Key Moments - 3 Insights

Why does the counter reset to max_value when it reaches zero?

Because the condition counter=0 is true at step 8 in the execution_table, triggering the reset action to max_value.

What happens if there is no clock rising edge?

As shown in the exit row of execution_table, no action occurs and the counter value stays the same.

Why do we check the condition before decrementing?

To avoid underflow and ensure the counter resets properly, as seen in steps 7 and 8 where counter reaches zero then resets.

Visual Quiz - 3 Questions

Look at the execution_table, what is the counter value after step 5?

A 2

B 3

C 4

D 5

💡 Hint

Check the 'counter after' column at step 5 in the execution_table.

At which step does the counter reset to max_value?

A Step 7

B Step 8

C Step 9

D Step 6

💡 Hint

Look for the row where condition counter=0 is Yes and action is reset in execution_table.

If the initial counter was 3 instead of 7, what would be the counter after step 3?

A 1

B 2

C 0

D 3

💡 Hint

Follow the decrement steps starting from 3 in variable_tracker.

Concept Snapshot

Binary down counter in VHDL:
- Starts at max_value
- On each clock rising edge:
  - If counter=0, reset to max_value
  - Else decrement by 1
- Outputs current counter value
- Repeats every clock cycle

Full Transcript

This visual execution trace shows a binary down counter in VHDL. The counter starts at a maximum value (7). On each rising edge of the clock signal, the counter checks if it is zero. If it is zero, it resets to the maximum value. Otherwise, it decreases by one. The output is the current counter value after each decrement or reset. The execution table traces each clock cycle step by step, showing the counter value before and after, the condition check, and the action taken. The variable tracker shows how the counter changes over time. Key moments clarify why the reset happens and what occurs if there is no clock edge. The quiz questions help reinforce understanding by referencing specific steps in the execution table and variable tracker.

Practice

1.

What does a binary down counter do in VHDL?

easy

A. Generates random binary numbers continuously

B. Counts forwards in decimal numbers on each clock pulse

C. Counts backwards in binary numbers on each clock pulse

D. Stores a fixed binary value without changing

Solution

1. Step 1: Understand the function of a down counter

   A down counter decreases its count value by one on each clock pulse, moving backwards in binary.

2. Step 2: Compare options with definition

   Only Counts backwards in binary numbers on each clock pulse describes counting backwards in binary on clock pulses, matching the down counter behavior.

3. Final Answer:

   Counts backwards in binary numbers on each clock pulse -> Option C

4. Quick Check:

   Down counter = counts backwards [OK]

Hint: Down counter always decreases count on clock pulse [OK]

Common Mistakes:

• Confusing down counter with up counter
• Thinking it counts in decimal
• Assuming it holds a fixed value

2.

Which of the following is the correct VHDL syntax to declare a 4-bit binary down counter signal?

signal count : ?;

easy

A. std_logic_vector(3 downto 0)

B. integer range 0 to 15

C. bit_vector(0 to 3)

D. std_logic_vector(0 to 3)

Solution

1. Step 1: Identify correct vector type and direction

   For a 4-bit binary counter, std_logic_vector(3 downto 0) is standard to represent bits from MSB to LSB.

2. Step 2: Check other options for correctness

   The integer range uses integer, not vector; bit_vector with ascending range is less common; std_logic_vector(0 to 3) uses ascending range which is unusual for counters.

3. Final Answer:

   std_logic_vector(3 downto 0) -> Option A

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Using ascending range instead of downto
• Confusing bit_vector with std_logic_vector

3.

Given this VHDL process for a 3-bit down counter starting at 7:

process(clk, reset)
begin
  if reset = '1' then
    count <= "111";
  elsif rising_edge(clk) then
    count <= count - 1;
  end if;
end process;

What is the value of count after 3 clock pulses (assuming reset is '0')?

medium

A. "101"

B. "100"

C. "011"

D. "110"

Solution

1. Step 1: Start from initial value after reset

   Reset sets count to "111" which is decimal 7.

2. Step 2: Subtract 1 on each clock pulse for 3 pulses

   7 - 1 = 6 ("110"), 6 - 1 = 5 ("101"), 5 - 1 = 4 ("100").

3. Final Answer:

   "100" -> Option B

4. Quick Check:

   7 - 3 = 4 = "100" [OK]

Hint: Subtract 1 per clock pulse from start value [OK]

Common Mistakes:

• Counting up instead of down
• Misinterpreting binary values
• Forgetting reset sets initial value

4.

Identify the error in this VHDL down counter process:

process(clk, reset)
begin
  if reset = '1' then
    count <= "1111";
  elsif clk'event and clk = '1' then
    count <= count + 1;
  end if;
end process;

medium

A. Reset value is incorrect for 4 bits

B. Missing signal declaration for count

C. Clock edge detection syntax is wrong

D. Counter counts up instead of down

Solution

1. Step 1: Analyze counting operation

   The process increments count with count + 1, which is counting up, not down.

2. Step 2: Verify other parts for errors

   Reset value "1111" is valid for 4 bits; clock edge detection syntax is correct; signal declaration is not shown but not necessarily an error here.

3. Final Answer:

   Counter counts up instead of down -> Option D

4. Quick Check:

   Down counter must decrement, not increment [OK]

Hint: Down counter subtracts 1, not adds 1 [OK]

Common Mistakes:

• Using count + 1 instead of count - 1
• Confusing clock edge syntax
• Ignoring reset value correctness

5.

You want to design a 5-bit binary down counter in VHDL that resets to 31 and stops counting when it reaches 0. Which approach correctly implements this behavior?

hard

A. Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count

B. Reset count to 0; on clock, count <= count - 1 unconditionally

C. Reset count to "00000"; on clock, if count < 31 then count <= count + 1

D. Reset count to "11111"; on clock, count <= count + 1 until 31

Solution

1. Step 1: Set initial count and stopping condition

   Reset to "11111" (decimal 31) is correct for 5 bits; stopping at 0 means counting down until zero.

2. Step 2: Implement conditional decrement

   On each clock, decrement only if count > 0; else hold count to stop at zero.

3. Final Answer:

   Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count -> Option A

4. Quick Check:

   Count down from 31 to 0, stop at 0 [OK]

Hint: Decrement only if count > 0 to stop at zero [OK]

Common Mistakes:

• Resetting to zero instead of max value
• Counting up instead of down
• Not stopping at zero, causing underflow