Binary down counter in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 3-bit binary down counter after 5 clock cycles

Consider a 3-bit binary down counter initialized to "111" (decimal 7). It decrements by 1 on each clock cycle. What is the output value after 5 clock cycles?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity down_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR (2 downto 0));
end down_counter;

architecture Behavioral of down_counter is
    signal cnt : unsigned(2 downto 0) := "111";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            cnt <= "111";
        elsif rising_edge(clk) then
            cnt <= cnt - 1;
        end if;
    end process;
    count <= std_logic_vector(cnt);
end Behavioral;

A "010"

B "011"

C "100"

D "101"

💡 Hint

Count down from 7 by 1, five times: 7, 6, 5, 4, 3, 2...

The counter starts at 7 (binary 111). After 5 decrements, it reaches 2, which is binary "010".

🧠 Conceptual

intermediate

Behavior of a synchronous reset in a binary down counter

In a binary down counter with a synchronous reset, what happens when the reset signal is asserted during a clock edge?

A The counter resets only after several clock cycles.

B The counter resets asynchronously, ignoring the clock edge.

C The counter continues counting without resetting until the reset is deasserted.

D The counter resets to its initial value immediately at the clock edge.

💡 Hint

Think about what synchronous means: reset happens in sync with the clock.

A synchronous reset means the counter resets its value only at the clock edge when the reset signal is high.

🔧 Debug

advanced

Identify the error in this binary down counter VHDL code

What error will this VHDL code produce when synthesized or simulated?

VHDL

process(clk, reset)
begin
    if reset = '1' then
        cnt <= "000";
    elsif rising_edge(clk) then
        cnt <= cnt - 1;
    end if;
end process;

A Simulation error because 'clk'event is deprecated; use rising_edge(clk).

B Synthesis error due to missing library for unsigned arithmetic.

C No error, code works correctly.

D Runtime error because cnt is not declared.

💡 Hint

Check the recommended way to detect clock edges in VHDL.

Using 'clk'event and clk = '1' is legal but discouraged; modern VHDL uses rising_edge(clk) for clarity and synthesis compatibility.

📝 Syntax

advanced

Syntax error in VHDL binary down counter process

Which option contains the correct syntax for a process that decrements a 4-bit unsigned counter on the rising edge of clk with asynchronous reset?

A

process(clk, reset)
begin
  if reset = '1' then
    cnt <= (others => '0')
  elsif rising_edge(clk) then
    cnt <= cnt - 1;
  end if;
end process;

B

process(clk, reset)
begin
  if reset = '1' then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt - 1;
  end if
end process;

C

process(clk, reset)
begin
  if reset = '1' then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt - 1;
  end if;
end process;

D

process(clk, reset)
begin
  if reset = '1' then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt - 1
  end if;
end process;

💡 Hint

Check for missing semicolons and proper end if statement.

Option C has all semicolons properly placed after every statement including after 'end if;'. Option C misses semicolon after 'end if'. Option C misses semicolon after the reset assignment. Option C misses semicolon after the decrement assignment 'cnt <= cnt - 1'.

🚀 Application

expert

Number of distinct states in a 5-bit binary down counter with wrap-around

A 5-bit binary down counter counts down from 31 to 0 and then wraps around back to 31. How many distinct states does this counter have before repeating?

A 31

B 32

C 30

D 33

💡 Hint

Think about how many values a 5-bit binary number can represent.

A 5-bit binary number can represent 2^5 = 32 distinct values, from 0 to 31 inclusive.

Practice

1.

What does a binary down counter do in VHDL?

easy

A. Generates random binary numbers continuously

B. Counts forwards in decimal numbers on each clock pulse

C. Counts backwards in binary numbers on each clock pulse

D. Stores a fixed binary value without changing

Solution

1. Step 1: Understand the function of a down counter

   A down counter decreases its count value by one on each clock pulse, moving backwards in binary.

2. Step 2: Compare options with definition

   Only Counts backwards in binary numbers on each clock pulse describes counting backwards in binary on clock pulses, matching the down counter behavior.

3. Final Answer:

   Counts backwards in binary numbers on each clock pulse -> Option C

4. Quick Check:

   Down counter = counts backwards [OK]

Hint: Down counter always decreases count on clock pulse [OK]

Common Mistakes:

• Confusing down counter with up counter
• Thinking it counts in decimal
• Assuming it holds a fixed value

2.

Which of the following is the correct VHDL syntax to declare a 4-bit binary down counter signal?

signal count : ?;

easy

A. std_logic_vector(3 downto 0)

B. integer range 0 to 15

C. bit_vector(0 to 3)

D. std_logic_vector(0 to 3)

Solution

1. Step 1: Identify correct vector type and direction

   For a 4-bit binary counter, std_logic_vector(3 downto 0) is standard to represent bits from MSB to LSB.

2. Step 2: Check other options for correctness

   The integer range uses integer, not vector; bit_vector with ascending range is less common; std_logic_vector(0 to 3) uses ascending range which is unusual for counters.

3. Final Answer:

   std_logic_vector(3 downto 0) -> Option A

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Using ascending range instead of downto
• Confusing bit_vector with std_logic_vector

3.

Given this VHDL process for a 3-bit down counter starting at 7:

process(clk, reset)
begin
  if reset = '1' then
    count <= "111";
  elsif rising_edge(clk) then
    count <= count - 1;
  end if;
end process;

What is the value of count after 3 clock pulses (assuming reset is '0')?

medium

A. "101"

B. "100"

C. "011"

D. "110"

Solution

1. Step 1: Start from initial value after reset

   Reset sets count to "111" which is decimal 7.

2. Step 2: Subtract 1 on each clock pulse for 3 pulses

   7 - 1 = 6 ("110"), 6 - 1 = 5 ("101"), 5 - 1 = 4 ("100").

3. Final Answer:

   "100" -> Option B

4. Quick Check:

   7 - 3 = 4 = "100" [OK]

Hint: Subtract 1 per clock pulse from start value [OK]

Common Mistakes:

• Counting up instead of down
• Misinterpreting binary values
• Forgetting reset sets initial value

4.

Identify the error in this VHDL down counter process:

process(clk, reset)
begin
  if reset = '1' then
    count <= "1111";
  elsif clk'event and clk = '1' then
    count <= count + 1;
  end if;
end process;

medium

A. Reset value is incorrect for 4 bits

B. Missing signal declaration for count

C. Clock edge detection syntax is wrong

D. Counter counts up instead of down

Solution

1. Step 1: Analyze counting operation

   The process increments count with count + 1, which is counting up, not down.

2. Step 2: Verify other parts for errors

   Reset value "1111" is valid for 4 bits; clock edge detection syntax is correct; signal declaration is not shown but not necessarily an error here.

3. Final Answer:

   Counter counts up instead of down -> Option D

4. Quick Check:

   Down counter must decrement, not increment [OK]

Hint: Down counter subtracts 1, not adds 1 [OK]

Common Mistakes:

• Using count + 1 instead of count - 1
• Confusing clock edge syntax
• Ignoring reset value correctness

5.

You want to design a 5-bit binary down counter in VHDL that resets to 31 and stops counting when it reaches 0. Which approach correctly implements this behavior?

hard

A. Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count

B. Reset count to 0; on clock, count <= count - 1 unconditionally

C. Reset count to "00000"; on clock, if count < 31 then count <= count + 1

D. Reset count to "11111"; on clock, count <= count + 1 until 31

Solution

1. Step 1: Set initial count and stopping condition

   Reset to "11111" (decimal 31) is correct for 5 bits; stopping at 0 means counting down until zero.

2. Step 2: Implement conditional decrement

   On each clock, decrement only if count > 0; else hold count to stop at zero.

3. Final Answer:

   Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count -> Option A

4. Quick Check:

   Count down from 31 to 0, stop at 0 [OK]

Hint: Decrement only if count > 0 to stop at zero [OK]

Common Mistakes:

• Resetting to zero instead of max value
• Counting up instead of down
• Not stopping at zero, causing underflow