Binary down counter in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit down counter signal.

VHDL

signal counter : std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A0

B3

C4

D7

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 instead of 3 as the highest index.

Confusing the direction of the range.

The counter is 4 bits wide, so the highest index is 3 (0 to 3).

2fill in blank

medium

Complete the process sensitivity list to trigger on clock and reset signals.

VHDL

process([1])

Drag options to blanks, or click blank then click option'

Aclk, reset

Breset, clk

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Including only one signal in the sensitivity list.

Listing signals in the wrong order.

The process should be sensitive to both clock and reset signals, listed as clk, reset.

3fill in blank

hard

Fix the error in the if statement checking for reset being active high.

VHDL

if [1] = '1' then

Drag options to blanks, or click blank then click option'

Areset_n

Bclk

Cenable

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset_n which is active low instead of reset.

Checking clock or enable signals instead of reset.

The reset signal is active high, so the condition should check if reset = '1'.

4fill in blank

hard

Fill both blanks to correctly decrement the counter and reset it to 15 when it reaches 0.

VHDL

if counter = [1] then
    counter <= [2];
else
    counter <= counter - 1;
end if;

Drag options to blanks, or click blank then click option'

A"0000"

B"1111"

C"0001"

D"1110"

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong binary values for reset or zero.

Confusing increment with decrement logic.

The counter resets to 15 ("1111") when it reaches 0 ("0000").

5fill in blank

hard

Fill all three blanks to complete the process that updates the counter on the rising edge of the clock and handles reset.

VHDL

process(clk, reset)
begin
    if [1] = '1' then
        counter <= [2];
    elsif rising_edge([3]) then
        counter <= counter - 1;
    end if;
end process;

Drag options to blanks, or click blank then click option'

Areset

B"1111"

Cclk

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using enable instead of clk in rising_edge.

Resetting counter to wrong value.

Checking reset after clock edge.

The process resets the counter to 15 when reset is high, and decrements on the rising edge of clk.

Practice

1.

What does a binary down counter do in VHDL?

easy

A. Generates random binary numbers continuously

B. Counts forwards in decimal numbers on each clock pulse

C. Counts backwards in binary numbers on each clock pulse

D. Stores a fixed binary value without changing

Solution

1. Step 1: Understand the function of a down counter

   A down counter decreases its count value by one on each clock pulse, moving backwards in binary.

2. Step 2: Compare options with definition

   Only Counts backwards in binary numbers on each clock pulse describes counting backwards in binary on clock pulses, matching the down counter behavior.

3. Final Answer:

   Counts backwards in binary numbers on each clock pulse -> Option C

4. Quick Check:

   Down counter = counts backwards [OK]

Hint: Down counter always decreases count on clock pulse [OK]

Common Mistakes:

• Confusing down counter with up counter
• Thinking it counts in decimal
• Assuming it holds a fixed value

2.

Which of the following is the correct VHDL syntax to declare a 4-bit binary down counter signal?

signal count : ?;

easy

A. std_logic_vector(3 downto 0)

B. integer range 0 to 15

C. bit_vector(0 to 3)

D. std_logic_vector(0 to 3)

Solution

1. Step 1: Identify correct vector type and direction

   For a 4-bit binary counter, std_logic_vector(3 downto 0) is standard to represent bits from MSB to LSB.

2. Step 2: Check other options for correctness

   The integer range uses integer, not vector; bit_vector with ascending range is less common; std_logic_vector(0 to 3) uses ascending range which is unusual for counters.

3. Final Answer:

   std_logic_vector(3 downto 0) -> Option A

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Using ascending range instead of downto
• Confusing bit_vector with std_logic_vector

3.

Given this VHDL process for a 3-bit down counter starting at 7:

process(clk, reset)
begin
  if reset = '1' then
    count <= "111";
  elsif rising_edge(clk) then
    count <= count - 1;
  end if;
end process;

What is the value of count after 3 clock pulses (assuming reset is '0')?

medium

A. "101"

B. "100"

C. "011"

D. "110"

Solution

1. Step 1: Start from initial value after reset

   Reset sets count to "111" which is decimal 7.

2. Step 2: Subtract 1 on each clock pulse for 3 pulses

   7 - 1 = 6 ("110"), 6 - 1 = 5 ("101"), 5 - 1 = 4 ("100").

3. Final Answer:

   "100" -> Option B

4. Quick Check:

   7 - 3 = 4 = "100" [OK]

Hint: Subtract 1 per clock pulse from start value [OK]

Common Mistakes:

• Counting up instead of down
• Misinterpreting binary values
• Forgetting reset sets initial value

4.

Identify the error in this VHDL down counter process:

process(clk, reset)
begin
  if reset = '1' then
    count <= "1111";
  elsif clk'event and clk = '1' then
    count <= count + 1;
  end if;
end process;

medium

A. Reset value is incorrect for 4 bits

B. Missing signal declaration for count

C. Clock edge detection syntax is wrong

D. Counter counts up instead of down

Solution

1. Step 1: Analyze counting operation

   The process increments count with count + 1, which is counting up, not down.

2. Step 2: Verify other parts for errors

   Reset value "1111" is valid for 4 bits; clock edge detection syntax is correct; signal declaration is not shown but not necessarily an error here.

3. Final Answer:

   Counter counts up instead of down -> Option D

4. Quick Check:

   Down counter must decrement, not increment [OK]

Hint: Down counter subtracts 1, not adds 1 [OK]

Common Mistakes:

• Using count + 1 instead of count - 1
• Confusing clock edge syntax
• Ignoring reset value correctness

5.

You want to design a 5-bit binary down counter in VHDL that resets to 31 and stops counting when it reaches 0. Which approach correctly implements this behavior?

hard

A. Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count

B. Reset count to 0; on clock, count <= count - 1 unconditionally

C. Reset count to "00000"; on clock, if count < 31 then count <= count + 1

D. Reset count to "11111"; on clock, count <= count + 1 until 31

Solution

1. Step 1: Set initial count and stopping condition

   Reset to "11111" (decimal 31) is correct for 5 bits; stopping at 0 means counting down until zero.

2. Step 2: Implement conditional decrement

   On each clock, decrement only if count > 0; else hold count to stop at zero.

3. Final Answer:

   Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count -> Option A

4. Quick Check:

   Count down from 31 to 0, stop at 0 [OK]

Hint: Decrement only if count > 0 to stop at zero [OK]

Common Mistakes:

• Resetting to zero instead of max value
• Counting up instead of down
• Not stopping at zero, causing underflow