Why structural design builds hierarchy in VHDL - Visual Breakdown

Concept Flow - Why structural design builds hierarchy

Start with top-level entity

↓

Instantiate components inside

↓

Connect components with signals

↓

Each component can have subcomponents

↓

Build deeper levels of hierarchy

↓

Final design is a tree of modules

Structural design in VHDL builds a hierarchy by instantiating components inside other components, connecting them with signals, and repeating this to form a tree-like structure.

Execution Sample

VHDL

entity Top is
end entity Top;
architecture Struct of Top is
  component Sub;
  end component;
begin
  U1: Sub port map();
end Struct;

This code shows a top-level entity instantiating a subcomponent, building a hierarchy.

Execution Table

Step	Action	Component/Entity	Result
1	Define top-level entity	Top	Entity Top created
2	Define component Sub	Sub	Component Sub declared inside architecture
3	Instantiate Sub as U1	U1: Sub	Instance U1 created inside Top
4	Connect signals (if any)	Signals	Signals connect U1 ports (none here)
5	Hierarchy formed	Top -> U1	Top contains U1, building hierarchy
6	End architecture	Struct	Structural design complete

💡 All components instantiated and connected, hierarchy built

Variable Tracker

Variable	Start	After 1	After 2	After 3	Final
Top entity	undefined	defined	defined	defined	defined with U1 instance
Sub component	undefined	undefined	declared	declared	declared
U1 instance	undefined	undefined	undefined	created	created inside Top

Key Moments - 3 Insights

Why do we instantiate components inside other components?

Because instantiating components inside others creates a hierarchy, as shown in execution_table row 3 where U1 is created inside Top.

How does connecting signals relate to hierarchy?

Signals connect components but do not flatten hierarchy; they link instances inside the structure, as in execution_table row 4.

Can a component have subcomponents?

Yes, components can instantiate other components, building deeper hierarchy levels, as described in concept_flow.

Visual Quiz - 3 Questions

Look at the execution table, at which step is the subcomponent instantiated inside the top entity?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Check the 'Action' and 'Result' columns in execution_table row 3 for instantiation details.

According to variable_tracker, what is the state of the U1 instance after step 3?

A Created inside Top

B Undefined

C Declared but not created

D Deleted

💡 Hint

Look at the 'U1 instance' row and the 'After 3' column in variable_tracker.

If we add signals connecting U1 ports, which step in the execution_table would change?

A Step 2

B Step 4

C Step 3

D Step 6

💡 Hint

Step 4 in execution_table mentions connecting signals.

Concept Snapshot

Structural design in VHDL builds hierarchy by:
- Defining entities and components
- Instantiating components inside others
- Connecting them with signals
- Repeating to form a tree structure
This helps organize complex designs clearly.

Full Transcript

In VHDL structural design, you start by defining a top-level entity. Inside its architecture, you declare components. Then you instantiate these components inside the top-level entity, creating instances. These instances can be connected with signals. This process builds a hierarchy, like a tree, where the top entity contains subcomponents, which can themselves contain further subcomponents. This hierarchy helps organize and manage complex hardware designs clearly and modularly.

Practice

1. Why does structural design in VHDL build hierarchy?

easy

A. To avoid using components and signals

B. To break a complex circuit into smaller, manageable blocks

C. To write all code in a single block without submodules

D. To make the design run faster without any blocks

Solution

1. Step 1: Understand structural design purpose

   Structural design divides a big circuit into smaller blocks for clarity and manageability.

2. Step 2: Recognize hierarchy role

   Hierarchy shows how these smaller blocks connect to form the full design.

3. Final Answer:

   To break a complex circuit into smaller, manageable blocks -> Option B

4. Quick Check:

   Structural design = smaller blocks [OK]

Hint: Hierarchy means breaking big design into smaller parts [OK]

Common Mistakes:

• Thinking hierarchy means faster speed
• Believing all code stays in one block
• Ignoring the use of components

2. Which VHDL syntax correctly instantiates a component to build hierarchy?

easy

A. process(clk) begin if clk='1' then ... end if; end process;

B. component my_block is port(clk, rst); end component;

C. signal clk, rst: std_logic;

D. U1: entity work.my_block port map(clk => clk, rst => rst)

Solution

1. Step 1: Identify component instantiation syntax

   Instantiating a component uses label: entity work.entity_name port map(...).

2. Step 2: Check options for correct instantiation

   U1: entity work.my_block port map(clk => clk, rst => rst) matches correct instantiation syntax with label U1 and port map.

3. Final Answer:

   U1: entity work.my_block port map(clk => clk, rst => rst) -> Option D

4. Quick Check:

   Component instantiation = label: entity work.name port map [OK]

Hint: Look for 'label: entity work.name port map' pattern [OK]

Common Mistakes:

• Confusing component declaration with instantiation
• Using signal declaration as instantiation
• Mixing process code with component instantiation

3. Given this VHDL structural code snippet, what is the output signal out_sig if in_sig is '1'?

entity top is
  port(in_sig: in std_logic; out_sig: out std_logic);
end top;

architecture structural of top is
  component inverter
    port(a: in std_logic; y: out std_logic);
  end component;
  signal temp: std_logic;
begin
  U1: inverter port map(a => in_sig, y => temp);
  U2: inverter port map(a => temp, y => out_sig);
end structural;

architecture behavioral of inverter is
begin
  y <= not a;
end behavioral;

medium

A. Undefined

B. '0'

C. '1'

D. Signal conflict error

Solution

1. Step 1: Trace first inverter output

   Input '1' to first inverter outputs '0' (not '1').

2. Step 2: Trace second inverter output

   Second inverter input '0' outputs '1' (not '0').

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Two NOT gates invert twice = original input [OK]

Hint: Two inverters cancel out, output equals input [OK]

Common Mistakes:

• Assuming output is '0' after first inverter
• Ignoring second inverter effect
• Thinking signal conflict occurs

4. Identify the error in this structural VHDL snippet:

architecture structural of top is
  component and_gate
    port(a, b: in std_logic; y: out std_logic);
  end component;
  signal s1, s2: std_logic;
begin
  U1: and_gate port map(a => s1, b => s2, y => s3);
end structural;

medium

A. Signal s3 is not declared

B. Component and_gate missing port map

C. Signals s1 and s2 are not declared

D. Architecture name is missing

Solution

1. Step 1: Check signal declarations

   Signals s1 and s2 are declared, but s3 is used without declaration.

2. Step 2: Verify component instantiation

   Component and_gate is instantiated correctly with port map, but output signal s3 is undeclared.

3. Final Answer:

   Signal s3 is not declared -> Option A

4. Quick Check:

   Undeclared signal in port map = error [OK]

Hint: Check all signals used in port map are declared [OK]

Common Mistakes:

• Assuming missing signal is okay
• Confusing component declaration with instantiation
• Ignoring architecture header

5. How does structural design hierarchy help when fixing a large VHDL project with many components?

hard

A. It isolates problems to specific blocks, making debugging easier

B. It forces rewriting the entire code for any change

C. It removes the need for signals between components

D. It automatically optimizes the circuit speed

Solution

1. Step 1: Understand hierarchy benefit

   Hierarchy breaks design into blocks, so errors can be found in smaller parts.

2. Step 2: Relate to debugging ease

   Isolating problems to blocks avoids searching entire code, speeding fixes.

3. Final Answer:

   It isolates problems to specific blocks, making debugging easier -> Option A

4. Quick Check:

   Hierarchy helps isolate bugs [OK]

Hint: Fix blocks one by one, not whole design [OK]

Common Mistakes:

• Thinking hierarchy forces full rewrite
• Believing signals are unnecessary
• Assuming automatic speed optimization