Why structural design builds hierarchy in VHDL - See It in Action

Why Structural Design Builds Hierarchy

📖 Scenario: Imagine you are designing a simple digital system using VHDL. To keep your design clear and organized, you want to build it step-by-step by connecting smaller parts together. This approach is called structural design, and it helps create a hierarchy where small components combine to form bigger components.

🎯 Goal: You will create a small VHDL project that shows how structural design builds hierarchy by connecting simple components into a bigger system.

📋 What You'll Learn

Create a simple AND gate component

Create a simple OR gate component

Create a top-level component that uses the AND and OR components

Show how the top-level component connects the smaller components structurally

💡 Why This Matters

🌍 Real World

Structural design is used in real digital circuit design to organize complex systems into manageable parts, making designs easier to understand and maintain.

💼 Career

Understanding structural design and hierarchy is essential for hardware engineers and FPGA developers who build and test digital circuits using VHDL.

1

Create an AND gate component

Write a VHDL entity and architecture for an AND gate called AndGate with two inputs A and B and one output Y. Use the and operator inside the architecture to assign Y.

VHDL

-- Your code here to create AndGate entity and architecture

Hint

Remember to define inputs and outputs in the entity, then use Y <= A and B; in the architecture.

2

Create an OR gate component

Write a VHDL entity and architecture for an OR gate called OrGate with two inputs A and B and one output Y. Use the or operator inside the architecture to assign Y. Include the complete code below the AndGate code.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

-- Your code here to create OrGate entity and architecture

Hint

Follow the same pattern as AndGate but use or operator.

3

Create a top-level component using AndGate and OrGate

Write a VHDL entity and architecture called TopLevel with three inputs A, B, C and one output Y. Inside the architecture, declare signals to connect the AndGate and OrGate components. Instantiate AndGate and OrGate components and connect them so that AndGate takes A and B, OrGate takes the output of AndGate and C, and the output of OrGate is Y. Use structural design style with component declarations and port map.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

entity OrGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end OrGate;

architecture Behavioral of OrGate is
begin
    Y <= A or B;
end Behavioral;

-- Your code here to create TopLevel entity and architecture with component instantiations

Hint

Declare signals to connect components. Use component declarations and port map to connect inputs and outputs.

4

Simulate and display the output connections

Write a simple testbench process inside the TopLevel architecture that assigns values to inputs A, B, and C and prints the output Y to the console using report statements. Assign A = '1', B = '0', and C = '1'. Then print the value of Y.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y  A, B => B, Y => and_out);
    U2: OrGate port map (A => and_out, B => C, Y => Y);

    process
    begin
        -- Your code here to assign inputs and report output
    end process;
end Structural;

Hint

Use a process to assign inputs and use report to print the output value.

Practice

1. Why does structural design in VHDL build hierarchy?

easy

A. To avoid using components and signals

B. To break a complex circuit into smaller, manageable blocks

C. To write all code in a single block without submodules

D. To make the design run faster without any blocks

Solution

1. Step 1: Understand structural design purpose

   Structural design divides a big circuit into smaller blocks for clarity and manageability.

2. Step 2: Recognize hierarchy role

   Hierarchy shows how these smaller blocks connect to form the full design.

3. Final Answer:

   To break a complex circuit into smaller, manageable blocks -> Option B

4. Quick Check:

   Structural design = smaller blocks [OK]

Hint: Hierarchy means breaking big design into smaller parts [OK]

Common Mistakes:

• Thinking hierarchy means faster speed
• Believing all code stays in one block
• Ignoring the use of components

2. Which VHDL syntax correctly instantiates a component to build hierarchy?

easy

A. process(clk) begin if clk='1' then ... end if; end process;

B. component my_block is port(clk, rst); end component;

C. signal clk, rst: std_logic;

D. U1: entity work.my_block port map(clk => clk, rst => rst)

Solution

1. Step 1: Identify component instantiation syntax

   Instantiating a component uses label: entity work.entity_name port map(...).

2. Step 2: Check options for correct instantiation

   U1: entity work.my_block port map(clk => clk, rst => rst) matches correct instantiation syntax with label U1 and port map.

3. Final Answer:

   U1: entity work.my_block port map(clk => clk, rst => rst) -> Option D

4. Quick Check:

   Component instantiation = label: entity work.name port map [OK]

Hint: Look for 'label: entity work.name port map' pattern [OK]

Common Mistakes:

• Confusing component declaration with instantiation
• Using signal declaration as instantiation
• Mixing process code with component instantiation

3. Given this VHDL structural code snippet, what is the output signal out_sig if in_sig is '1'?

entity top is
  port(in_sig: in std_logic; out_sig: out std_logic);
end top;

architecture structural of top is
  component inverter
    port(a: in std_logic; y: out std_logic);
  end component;
  signal temp: std_logic;
begin
  U1: inverter port map(a => in_sig, y => temp);
  U2: inverter port map(a => temp, y => out_sig);
end structural;

architecture behavioral of inverter is
begin
  y <= not a;
end behavioral;

medium

A. Undefined

B. '0'

C. '1'

D. Signal conflict error

Solution

1. Step 1: Trace first inverter output

   Input '1' to first inverter outputs '0' (not '1').

2. Step 2: Trace second inverter output

   Second inverter input '0' outputs '1' (not '0').

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Two NOT gates invert twice = original input [OK]

Hint: Two inverters cancel out, output equals input [OK]

Common Mistakes:

• Assuming output is '0' after first inverter
• Ignoring second inverter effect
• Thinking signal conflict occurs

4. Identify the error in this structural VHDL snippet:

architecture structural of top is
  component and_gate
    port(a, b: in std_logic; y: out std_logic);
  end component;
  signal s1, s2: std_logic;
begin
  U1: and_gate port map(a => s1, b => s2, y => s3);
end structural;

medium

A. Signal s3 is not declared

B. Component and_gate missing port map

C. Signals s1 and s2 are not declared

D. Architecture name is missing

Solution

1. Step 1: Check signal declarations

   Signals s1 and s2 are declared, but s3 is used without declaration.

2. Step 2: Verify component instantiation

   Component and_gate is instantiated correctly with port map, but output signal s3 is undeclared.

3. Final Answer:

   Signal s3 is not declared -> Option A

4. Quick Check:

   Undeclared signal in port map = error [OK]

Hint: Check all signals used in port map are declared [OK]

Common Mistakes:

• Assuming missing signal is okay
• Confusing component declaration with instantiation
• Ignoring architecture header

5. How does structural design hierarchy help when fixing a large VHDL project with many components?

hard

A. It isolates problems to specific blocks, making debugging easier

B. It forces rewriting the entire code for any change

C. It removes the need for signals between components

D. It automatically optimizes the circuit speed

Solution

1. Step 1: Understand hierarchy benefit

   Hierarchy breaks design into blocks, so errors can be found in smaller parts.

2. Step 2: Relate to debugging ease

   Isolating problems to blocks avoids searching entire code, speeding fixes.

3. Final Answer:

   It isolates problems to specific blocks, making debugging easier -> Option A

4. Quick Check:

   Hierarchy helps isolate bugs [OK]

Hint: Fix blocks one by one, not whole design [OK]

Common Mistakes:

• Thinking hierarchy forces full rewrite
• Believing signals are unnecessary
• Assuming automatic speed optimization