Single-port RAM in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a RAM array of 16 locations, each 8 bits wide.

VHDL

type ram_type is array (0 to 15) of std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A0

B8

C15

D7

Attempts:

3 left

💡 Hint

Common Mistakes

Using 8 instead of 7 as the highest index.

Confusing the size of the array with the bit width.

The RAM has 8 bits per location, so the index goes from 7 down to 0.

2fill in blank

medium

Complete the code to declare a signal named ram of the RAM type.

VHDL

signal ram : [1];

Drag options to blanks, or click blank then click option'

Aram_type

Bstd_logic_vector(7 downto 0)

Cinteger

Dstd_logic

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic_vector instead of the RAM array type.

Using integer or std_logic which are not array types.

The signal ram must be declared with the RAM array type defined earlier.

3fill in blank

hard

Fix the error in the process sensitivity list to include the clock signal named clk.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- RAM write or read logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bdata_in

Caddress

Dwrite_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_in or address signals in the sensitivity list instead of clk.

Leaving the sensitivity list empty.

The process must be sensitive to the clock signal to detect rising edges.

4fill in blank

hard

Fill both blanks to write data_in to ram at address when write_enable is high.

VHDL

if [1] = '1' then
  ram([2]) <= data_in;
end if;

Drag options to blanks, or click blank then click option'

Awrite_enable

Bread_enable

Caddress

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using read_enable instead of write_enable.

Using clk instead of address for the RAM index.

Write happens when write_enable is '1' at the given address.

5fill in blank

hard

Fill both blanks to read ram at address into data_out.

VHDL

if rising_edge(clk) then
  if [1] = '0' then
    data_out <= ram([2]);
  end if;
end if;

Drag options to blanks, or click blank then click option'

Awrite_enable

Baddress

Cread_enable

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing write_enable and read_enable signals.

Using data_in instead of address for RAM indexing.

Reading occurs when write_enable is '0', reading from ram at address.

Practice

1. What is the main function of a single-port RAM in VHDL?

easy

A. Generate clock signals

B. Store data using one address and one data line

C. Perform arithmetic operations

D. Control input/output pins

Solution

1. Step 1: Understand the role of single-port RAM

   Single-port RAM is designed to store data at a specific address with one data input and output line.

2. Step 2: Identify the correct function

   It does not perform arithmetic, generate clocks, or control pins; it only stores and retrieves data.

3. Final Answer:

   Store data using one address and one data line -> Option B

4. Quick Check:

   Single-port RAM = Data storage [OK]

Hint: Single-port RAM stores data at one address line [OK]

Common Mistakes:

• Confusing RAM with arithmetic units
• Thinking RAM generates clocks
• Assuming RAM controls I/O pins

2. Which VHDL statement correctly declares a single-port RAM with 16 locations of 8-bit width?

easy

A. signal ram : std_logic_vector(7 downto 0) array (0 to 15);

B. signal ram : std_logic_vector(15 downto 0)(7 downto 0);

C. type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type;

D. type ram_type is array (7 downto 0) of std_logic_vector(0 to 15);\nsignal ram : ram_type;

Solution

1. Step 1: Understand array declaration syntax

   In VHDL, RAM is declared as an array of std_logic_vector with address range and data width.

2. Step 2: Check each option

   type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type; correctly declares an array from 0 to 15 with 8-bit vectors. Others have incorrect syntax or order.

3. Final Answer:

   type ram_type is array (0 to 15) of std_logic_vector(7 downto 0); signal ram : ram_type; -> Option C

4. Quick Check:

   Correct array declaration = type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type; [OK]

Hint: Use 'array (0 to N) of std_logic_vector(width downto 0)' [OK]

Common Mistakes:

• Reversing array and vector ranges
• Using incorrect syntax for array of vectors
• Declaring signal without type

3. Given this VHDL process for single-port RAM:

process(clk) begin
  if rising_edge(clk) then
    if we = '1' then
      ram(to_integer(unsigned(addr))) <= data_in;
    end if;
    data_out <= ram(to_integer(unsigned(addr)));
  end if;
end process;

What happens when we is '1' and addr is 3?

medium

A. Data at address 3 is updated but data_out shows old data

B. Data at address 3 is not updated but data_out shows old data

C. Data at address 3 is updated with data_in and data_out shows new data

D. No change occurs in RAM or output

Solution

1. Step 1: Analyze write operation timing

   On rising clock edge, if write enable (we) is '1', RAM at address is updated with data_in.

2. Step 2: Analyze read operation timing

   Data_out is assigned from RAM at address after write, but read happens before write completes, so old data is output.

3. Final Answer:

   Data at address 3 is updated but data_out shows old data -> Option A

4. Quick Check:

   Write updates RAM, read outputs old data [OK]

Hint: Write updates RAM, read outputs previous data same cycle [OK]

Common Mistakes:

• Assuming read shows new data immediately
• Confusing write enable effect
• Ignoring clock edge timing

4. Identify the error in this single-port RAM process:

process(clk) begin
  if clk'event and clk = '1' then
    if we = '1' then
      ram(addr) <= data_in;
    end if;
    data_out <= ram(addr);
  end if;
end process;

medium

A. Using clk'event and clk = '1' instead of rising_edge(clk)

B. No error, code is correct

C. Assigning data_out inside clocked process

D. Missing conversion from std_logic_vector to integer for addr

Solution

1. Step 1: Check clock edge detection

   Using clk'event and clk = '1' is valid but less recommended than rising_edge(clk).

2. Step 2: Check address usage

   Address 'addr' is likely std_logic_vector and must be converted to integer for RAM indexing.

3. Final Answer:

   Missing conversion from std_logic_vector to integer for addr -> Option D

4. Quick Check:

   Address must be integer index [OK]

Hint: Convert std_logic_vector addr to integer for RAM indexing [OK]

Common Mistakes:

• Using std_logic_vector directly as index
• Ignoring recommended rising_edge(clk)
• Thinking data_out can't be assigned in process

5. How would you modify a single-port RAM VHDL design to asynchronously clear all memory contents to zero on a reset signal?

hard

A. Add an asynchronous reset in the process that sets all RAM locations to zero

B. Use a synchronous reset that clears only the current address data

C. Add a separate process that writes zeros to RAM on reset clock edge

D. Reset signal cannot clear RAM contents in VHDL

Solution

1. Step 1: Understand asynchronous reset effect

   An asynchronous reset triggers immediately, allowing clearing all RAM locations regardless of clock.

2. Step 2: Implement reset logic

   Inside the clocked process, add a condition for reset that loops through all RAM addresses and sets them to zero.

3. Final Answer:

   Add an asynchronous reset in the process that sets all RAM locations to zero -> Option A

4. Quick Check:

   Async reset clears entire RAM [OK]

Hint: Use async reset to zero all RAM locations immediately [OK]

Common Mistakes:

• Clearing only one address on reset
• Using synchronous reset for full RAM clear
• Believing reset can't clear RAM