Single-port RAM in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process for a single-port RAM?

Consider a single-port RAM with 4 words of 8 bits each. The process below writes data when write_enable is '1' and reads data otherwise. What is the value of data_out after the rising edge of clk when write_enable='1', address=2, and data_in="10101010"?

VHDL

process(clk)
  type ram_type is array (0 to 3) of std_logic_vector(7 downto 0);
  variable ram : ram_type := (others => (others => '0'));
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      ram(to_integer(unsigned(address))) := data_in;
      data_out <= data_in;
    else
      data_out <= ram(to_integer(unsigned(address)));
    end if;
  end if;
end process;

A "00000000"

B "10101010"

C "11111111"

D "01010101"

💡 Hint

Remember that when write_enable is '1', the data is written and output immediately.

When write_enable is '1', the process writes data_in to the RAM at the given address and outputs data_in immediately on data_out.

❓ Predict Output

intermediate

What is the output of this VHDL code reading from single-port RAM?

Given the same RAM as before, if write_enable='0', address=1, and the RAM content at address 1 is "11001100", what will data_out be after the rising edge of clk?

VHDL

process(clk)
  type ram_type is array (0 to 3) of std_logic_vector(7 downto 0);
  variable ram : ram_type := ("00000000", "11001100", "10101010", "11110000");
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      ram(to_integer(unsigned(address))) := data_in;
      data_out <= data_in;
    else
      data_out <= ram(to_integer(unsigned(address)));
    end if;
  end if;
end process;

A "11001100"

B "00000000"

C "10101010"

D "11110000"

💡 Hint

When write_enable is '0', the RAM outputs the stored data at the address.

Since write_enable is '0', the process reads the RAM content at address 1, which is "11001100".

🔧 Debug

advanced

Identify the error in this single-port RAM VHDL code snippet

This VHDL code is intended to implement a single-port RAM. What error will occur when compiling or simulating this code?

VHDL

process(clk)
  type ram_type is array (0 to 3) of std_logic_vector(7 downto 0);
  variable ram : ram_type := (others => (others => '0'));
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      ram(address) := data_in;
      data_out <= data_in;
    else
      data_out <= ram(address);
    end if;
  end if;
end process;

A No error, code compiles and runs correctly

B Syntax error due to missing semicolon after variable declaration

C Runtime error because ram is not initialized

D Type mismatch error because 'address' is not converted to integer

💡 Hint

Check the type of 'address' and how it is used as an index.

The 'address' signal is usually a std_logic_vector and must be converted to integer using to_integer(unsigned(address)) before indexing the RAM array.

📝 Syntax

advanced

Which option correctly declares a single-port RAM signal in VHDL?

You want to declare a RAM signal with 16 words of 8 bits each. Which declaration is syntactically correct?

A

type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));

B signal ram : array (0 to 15) of std_logic_vector(7 downto 0) := (others => (others => '0'));

C

type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => '0');

D signal ram : std_logic_vector(7 downto 0) array (0 to 15) := (others => (others => '0'));

💡 Hint

Remember that arrays must be declared as types before signals can use them.

Option A correctly declares a type for the RAM array and then declares a signal of that type with initialization.

🚀 Application

expert

How many clock cycles are needed to write and then read a value from this single-port RAM?

Given a synchronous single-port RAM with one clock input, write_enable, address, data_in, and data_out signals, how many clock cycles does it take to write a value to address 5 and then read it back at address 5?

A 3 clock cycles

B 1 clock cycle

C 2 clock cycles

D 4 clock cycles

💡 Hint

Consider that writing happens on one clock edge and reading the updated data requires another clock edge.

Writing the data occurs on the first clock cycle when write_enable is '1'. Reading the data back requires the next clock cycle with write_enable '0' to output the stored value.

Practice

1. What is the main function of a single-port RAM in VHDL?

easy

A. Generate clock signals

B. Store data using one address and one data line

C. Perform arithmetic operations

D. Control input/output pins

Solution

1. Step 1: Understand the role of single-port RAM

   Single-port RAM is designed to store data at a specific address with one data input and output line.

2. Step 2: Identify the correct function

   It does not perform arithmetic, generate clocks, or control pins; it only stores and retrieves data.

3. Final Answer:

   Store data using one address and one data line -> Option B

4. Quick Check:

   Single-port RAM = Data storage [OK]

Hint: Single-port RAM stores data at one address line [OK]

Common Mistakes:

• Confusing RAM with arithmetic units
• Thinking RAM generates clocks
• Assuming RAM controls I/O pins

2. Which VHDL statement correctly declares a single-port RAM with 16 locations of 8-bit width?

easy

A. signal ram : std_logic_vector(7 downto 0) array (0 to 15);

B. signal ram : std_logic_vector(15 downto 0)(7 downto 0);

C. type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type;

D. type ram_type is array (7 downto 0) of std_logic_vector(0 to 15);\nsignal ram : ram_type;

Solution

1. Step 1: Understand array declaration syntax

   In VHDL, RAM is declared as an array of std_logic_vector with address range and data width.

2. Step 2: Check each option

   type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type; correctly declares an array from 0 to 15 with 8-bit vectors. Others have incorrect syntax or order.

3. Final Answer:

   type ram_type is array (0 to 15) of std_logic_vector(7 downto 0); signal ram : ram_type; -> Option C

4. Quick Check:

   Correct array declaration = type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);\nsignal ram : ram_type; [OK]

Hint: Use 'array (0 to N) of std_logic_vector(width downto 0)' [OK]

Common Mistakes:

• Reversing array and vector ranges
• Using incorrect syntax for array of vectors
• Declaring signal without type

3. Given this VHDL process for single-port RAM:

process(clk) begin
  if rising_edge(clk) then
    if we = '1' then
      ram(to_integer(unsigned(addr))) <= data_in;
    end if;
    data_out <= ram(to_integer(unsigned(addr)));
  end if;
end process;

What happens when we is '1' and addr is 3?

medium

A. Data at address 3 is updated but data_out shows old data

B. Data at address 3 is not updated but data_out shows old data

C. Data at address 3 is updated with data_in and data_out shows new data

D. No change occurs in RAM or output

Solution

1. Step 1: Analyze write operation timing

   On rising clock edge, if write enable (we) is '1', RAM at address is updated with data_in.

2. Step 2: Analyze read operation timing

   Data_out is assigned from RAM at address after write, but read happens before write completes, so old data is output.

3. Final Answer:

   Data at address 3 is updated but data_out shows old data -> Option A

4. Quick Check:

   Write updates RAM, read outputs old data [OK]

Hint: Write updates RAM, read outputs previous data same cycle [OK]

Common Mistakes:

• Assuming read shows new data immediately
• Confusing write enable effect
• Ignoring clock edge timing

4. Identify the error in this single-port RAM process:

process(clk) begin
  if clk'event and clk = '1' then
    if we = '1' then
      ram(addr) <= data_in;
    end if;
    data_out <= ram(addr);
  end if;
end process;

medium

A. Using clk'event and clk = '1' instead of rising_edge(clk)

B. No error, code is correct

C. Assigning data_out inside clocked process

D. Missing conversion from std_logic_vector to integer for addr

Solution

1. Step 1: Check clock edge detection

   Using clk'event and clk = '1' is valid but less recommended than rising_edge(clk).

2. Step 2: Check address usage

   Address 'addr' is likely std_logic_vector and must be converted to integer for RAM indexing.

3. Final Answer:

   Missing conversion from std_logic_vector to integer for addr -> Option D

4. Quick Check:

   Address must be integer index [OK]

Hint: Convert std_logic_vector addr to integer for RAM indexing [OK]

Common Mistakes:

• Using std_logic_vector directly as index
• Ignoring recommended rising_edge(clk)
• Thinking data_out can't be assigned in process

5. How would you modify a single-port RAM VHDL design to asynchronously clear all memory contents to zero on a reset signal?

hard

A. Add an asynchronous reset in the process that sets all RAM locations to zero

B. Use a synchronous reset that clears only the current address data

C. Add a separate process that writes zeros to RAM on reset clock edge

D. Reset signal cannot clear RAM contents in VHDL

Solution

1. Step 1: Understand asynchronous reset effect

   An asynchronous reset triggers immediately, allowing clearing all RAM locations regardless of clock.

2. Step 2: Implement reset logic

   Inside the clocked process, add a condition for reset that loops through all RAM addresses and sets them to zero.

3. Final Answer:

   Add an asynchronous reset in the process that sets all RAM locations to zero -> Option A

4. Quick Check:

   Async reset clears entire RAM [OK]

Hint: Use async reset to zero all RAM locations immediately [OK]

Common Mistakes:

• Clearing only one address on reset
• Using synchronous reset for full RAM clear
• Believing reset can't clear RAM