ROM using constant array in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a constant ROM array of 8 elements.

VHDL

type rom_array is array (0 to 7) of std_logic_vector(7 downto 0);
constant ROM : rom_array := ([1]);

Drag options to blanks, or click blank then click option'

A"00000000"

B"0000000", "0000001", "0000010", "0000011", "0000100", "0000101", "0000110", "0000111"

C"0", "1", "2", "3", "4", "5", "6", "7"

D"00000000", "00000001", "00000010", "00000011", "00000100", "00000101", "00000110", "00000111"

Attempts:

3 left

💡 Hint

Common Mistakes

Using 7-bit vectors instead of 8-bit.

Using single characters instead of 8-bit vectors.

Not enclosing elements in double quotes.

The ROM constant must be initialized with 8 elements of 8-bit std_logic_vector values.

2fill in blank

medium

Complete the code to read data from ROM at address 'addr'.

VHDL

process(addr) begin
  data_out <= ROM([1]);
end process;

Drag options to blanks, or click blank then click option'

Adata_out

Baddr

Caddr + 1

DROM

Attempts:

3 left

💡 Hint

Common Mistakes

Adding or subtracting from the address.

Using the output signal as index.

Using the ROM name instead of the address.

The ROM is indexed by the address signal 'addr' to output the stored data.

3fill in blank

hard

Fix the error in the ROM declaration by completing the missing part.

VHDL

constant ROM : rom_array := (0 => "00000001", 1 => "00000010", [1]);

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Aothers => "00000000"

Bothers => '0'

Cothers => 0

Dothers => "1"

Attempts:

3 left

💡 Hint

Common Mistakes

Using a single character instead of an 8-bit vector.

Using a character literal instead of a string.

Using a numeric zero without quotes.

The 'others' keyword fills all unspecified indices with the given 8-bit vector.

4fill in blank

hard

Fill both blanks to complete the ROM read process with synchronous clock.

VHDL

process(clk) begin
  if rising_edge(clk) then
    data_out <= ROM([1]);
  end if;
end process;

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Aaddr

Bdata_out

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or output signals as index.

Reading ROM outside the clocked process.

The ROM is read synchronously using the address signal 'addr' on clock rising edge.

5fill in blank

hard

Fill all three blanks to declare a ROM with 16 elements, initialize it, and read data synchronously.

VHDL

type rom_array is array (0 to 15) of std_logic_vector(7 downto 0);
constant ROM : rom_array := ([1]);
process(clk) begin
  if rising_edge(clk) then
    data_out <= ROM([2]);
  end if;
end process;

Drag options to blanks, or click blank then click option'

A"00000000", "00000001", "00000010", "00000011", "00000100", "00000101", "00000110", "00000111", "00001000", "00001001", "00001010", "00001011", "00001100", "00001101", "00001110", "00001111"

Baddr

Creset

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong number of elements in ROM initialization.

Using wrong signals for indexing or clock.

The ROM is initialized with 16 8-bit values, read synchronously on clock rising edge using 'addr'.

Practice

1. What is the main purpose of using a constant array to implement ROM in VHDL?

easy

A. To generate random data values dynamically

B. To create a writable memory block for data storage

C. To perform arithmetic operations on data

D. To store fixed data that can be read by address during simulation or synthesis

Solution

1. Step 1: Understand ROM functionality

   ROM (Read-Only Memory) stores fixed data that does not change during operation.

2. Step 2: Role of constant array in VHDL

   A constant array holds fixed values accessible by address, perfect for ROM implementation.

3. Final Answer:

   To store fixed data that can be read by address during simulation or synthesis -> Option D

4. Quick Check:

   ROM = fixed data storage [OK]

Hint: ROM stores fixed data accessed by address only [OK]

Common Mistakes:

• Confusing ROM with writable RAM
• Thinking ROM can be changed during runtime
• Using variable arrays instead of constant arrays

2. Which of the following is the correct way to declare a ROM using a constant array of 8-bit std_logic_vector in VHDL?

easy

A. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"04", x"08");

B. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := ("0000001", "0000010", "0000100", "0001000");

C. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := ("x01", "x02", "x04", "x08");

D. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (1, 2, 4, 8);

Solution

1. Step 1: Check array declaration syntax

   In VHDL, constant arrays must be declared with proper type and range, here 0 to 3 for 4 elements.

2. Step 2: Check value format for std_logic_vector

   Values must be std_logic_vector literals; hex notation x".." is correct for 8-bit vectors.

3. Final Answer:

   constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"04", x"08"); -> Option A

4. Quick Check:

   Hex literals with x".." for std_logic_vector [OK]

Hint: Use x".." for hex std_logic_vector constants [OK]

Common Mistakes:

• Using double quotes for hex values incorrectly
• Assigning integers directly to std_logic_vector
• Incorrect array type or syntax

3. Given the following VHDL ROM declaration and read process, what is the output on data_out when addr = "10" (binary 2)?

constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"0A", x"1B", x"2C", x"3D");

process(addr) begin
  data_out <= ROM(to_integer(unsigned(addr)));
end process;

medium

A. x"2C"

B. x"1B"

C. x"0A"

D. x"3D"

Solution

1. Step 1: Convert address to integer

   Address "10" in binary equals decimal 2.

2. Step 2: Access ROM at index 2

   ROM(2) is x"2C" as per the constant array declaration.

3. Final Answer:

   x"2C" -> Option A

4. Quick Check:

   addr 2 accesses ROM(2) = x"2C" [OK]

Hint: Convert binary address to integer to index ROM [OK]

Common Mistakes:

• Confusing binary "10" as decimal 10
• Using unsigned conversion incorrectly
• Accessing wrong ROM index

4. Identify the error in this VHDL ROM constant array declaration:

constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"03");

medium

A. Hex values must be in single quotes, not double quotes

B. ROM array size does not match the number of elements assigned

C. std_logic_vector cannot be used in constant arrays

D. ROM must be declared as a variable, not constant

Solution

1. Step 1: Check array range and element count

   Array declared from 0 to 3 means 4 elements expected.

2. Step 2: Count assigned elements

   Only 3 elements are assigned, causing a size mismatch error.

3. Final Answer:

   ROM array size does not match the number of elements assigned -> Option B

4. Quick Check:

   Array size must equal element count [OK]

Hint: Match array range with number of elements exactly [OK]

Common Mistakes:

• Assigning fewer elements than declared range
• Misusing quotes for hex literals
• Thinking constants can be variables

5. You want to create a 16-word ROM with 4-bit addresses and 8-bit data using a constant array in VHDL. Which of the following code snippets correctly implements this ROM and reads data based on the address input addr?

hard

A. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (others => (others => '0'));

process(addr) begin
data_out <= ROM(addr);
end process;

B. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0);

process(addr) begin
data_out <= ROM(addr);
end process;

C. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F");

process(addr) begin
data_out <= ROM(to_integer(unsigned(addr)));
end process;

D. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03");

process(addr) begin
data_out <= ROM(to_integer(unsigned(addr)));
end process;

Solution

1. Step 1: Check ROM declaration size and initialization

   ROM must have 16 elements (0 to 15) each 8-bit wide, fully initialized.

2. Step 2: Verify address conversion and data read

   Address is 4-bit std_logic_vector, converted to integer with to_integer(unsigned(addr)) to index ROM correctly.

3. Step 3: Validate code correctness

   constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; correctly initializes all 16 elements and reads data using proper address conversion.

4. Final Answer:

   constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; -> Option C

5. Quick Check:

   Full initialization + correct address indexing = constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; [OK]

Hint: Initialize all ROM elements and convert address to integer [OK]

Common Mistakes:

• Not initializing all ROM elements
• Using addr directly without conversion
• Declaring ROM without initialization