ROM using constant array in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of ROM read with constant array

What is the output on the data bus when the address input is 3 in this ROM implementation using a constant array?

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rom_const is
  port(
    addr : in std_logic_vector(2 downto 0);
    data : out std_logic_vector(7 downto 0)
  );
end rom_const;

architecture rtl of rom_const is
  type rom_array is array (0 to 7) of std_logic_vector(7 downto 0);
  constant rom_content : rom_array := (
    x"0A", x"1B", x"2C", x"3D", x"4E", x"5F", x"6A", x"7B"
  );
begin
  process(addr)
  begin
    data <= rom_content(to_integer(unsigned(addr)));
  end process;
end rtl;

A data = x"3D"

B data = x"2C"

C data = x"1B"

D data = x"4E"

💡 Hint

Remember that the address is converted from std_logic_vector to integer to index the array.

The address 3 corresponds to the fourth element in the constant array (indexing from 0). The value at index 3 is x"3D".

❓ Predict Output

intermediate

Value of data after address change

Given the ROM constant array below, what will be the value of 'data' when 'addr' is "101"?

VHDL

architecture rtl of rom_const is
  use ieee.numeric_std.all;
  type rom_array is array (0 to 7) of std_logic_vector(7 downto 0);
  constant rom_content : rom_array := (
    x"AA", x"BB", x"CC", x"DD", x"EE", x"FF", x"11", x"22"
  );
begin
  process(addr)
  begin
    data <= rom_content(to_integer(unsigned(addr)));
  end process;
end rtl;

A data = x"EE"

B data = x"DD"

C data = x"11"

D data = x"FF"

💡 Hint

Convert the binary address "101" to decimal to find the index.

The binary "101" is decimal 5. The value at index 5 in rom_content is x"FF".

🔧 Debug

advanced

Identify the error in ROM constant array declaration

What error will this VHDL code produce when compiling?

VHDL

architecture rtl of rom_const is
  type rom_array is array (0 to 7) of std_logic_vector(7 downto 0);
  constant rom_content : rom_array := (
    x"0A", x"1B", x"2C", x"3D", x"4E", x"5F", x"6A"
  );
begin
  process(addr)
  begin
    data <= rom_content(to_integer(unsigned(addr)));
  end process;
end rtl;

A Compilation error: array size mismatch

B Runtime error: index out of range

C No error, code compiles and runs correctly

D Syntax error: missing semicolon

💡 Hint

Check the number of elements in the constant array compared to its declared size.

The constant array is declared with 8 elements (0 to 7) but only 7 values are provided, causing a size mismatch error.

📝 Syntax

advanced

Correct syntax for ROM constant array initialization

Which option correctly initializes a constant ROM array of 4 elements with 8-bit values in VHDL?

A constant rom_content : rom_array := (x"01", x"02", x"03", x"04");

B constant rom_content : rom_array := (0 => x"01", 1 => x"02", 2 => x"03", 3 => x"04");

C constant rom_content : rom_array := [x"01", x"02", x"03", x"04"];

D constant rom_content : rom_array := {x"01", x"02", x"03", x"04"};

💡 Hint

VHDL uses parentheses with index associations for array initialization.

Option B uses the correct VHDL syntax with index associations. Option B misses index associations, C and D use invalid brackets.

🚀 Application

expert

Number of elements in ROM constant array

How many elements are in this ROM constant array?

VHDL

type rom_array is array (0 to 15) of std_logic_vector(7 downto 0);
constant rom_content : rom_array := (
  0 => x"00", 1 => x"11", 2 => x"22", 3 => x"33",
  4 => x"44", 5 => x"55", 6 => x"66", 7 => x"77",
  8 => x"88", 9 => x"99", 10 => x"AA", 11 => x"BB",
  12 => x"CC", 13 => x"DD", 14 => x"EE", 15 => x"FF"
);

A 15

B 14

C 16

D 8

💡 Hint

Count from 0 to 15 inclusive.

The array is declared from 0 to 15, which means it contains 16 elements in total.

Practice

1. What is the main purpose of using a constant array to implement ROM in VHDL?

easy

A. To generate random data values dynamically

B. To create a writable memory block for data storage

C. To perform arithmetic operations on data

D. To store fixed data that can be read by address during simulation or synthesis

Solution

1. Step 1: Understand ROM functionality

   ROM (Read-Only Memory) stores fixed data that does not change during operation.

2. Step 2: Role of constant array in VHDL

   A constant array holds fixed values accessible by address, perfect for ROM implementation.

3. Final Answer:

   To store fixed data that can be read by address during simulation or synthesis -> Option D

4. Quick Check:

   ROM = fixed data storage [OK]

Hint: ROM stores fixed data accessed by address only [OK]

Common Mistakes:

• Confusing ROM with writable RAM
• Thinking ROM can be changed during runtime
• Using variable arrays instead of constant arrays

2. Which of the following is the correct way to declare a ROM using a constant array of 8-bit std_logic_vector in VHDL?

easy

A. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"04", x"08");

B. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := ("0000001", "0000010", "0000100", "0001000");

C. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := ("x01", "x02", "x04", "x08");

D. constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (1, 2, 4, 8);

Solution

1. Step 1: Check array declaration syntax

   In VHDL, constant arrays must be declared with proper type and range, here 0 to 3 for 4 elements.

2. Step 2: Check value format for std_logic_vector

   Values must be std_logic_vector literals; hex notation x".." is correct for 8-bit vectors.

3. Final Answer:

   constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"04", x"08"); -> Option A

4. Quick Check:

   Hex literals with x".." for std_logic_vector [OK]

Hint: Use x".." for hex std_logic_vector constants [OK]

Common Mistakes:

• Using double quotes for hex values incorrectly
• Assigning integers directly to std_logic_vector
• Incorrect array type or syntax

3. Given the following VHDL ROM declaration and read process, what is the output on data_out when addr = "10" (binary 2)?

constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"0A", x"1B", x"2C", x"3D");

process(addr) begin
  data_out <= ROM(to_integer(unsigned(addr)));
end process;

medium

A. x"2C"

B. x"1B"

C. x"0A"

D. x"3D"

Solution

1. Step 1: Convert address to integer

   Address "10" in binary equals decimal 2.

2. Step 2: Access ROM at index 2

   ROM(2) is x"2C" as per the constant array declaration.

3. Final Answer:

   x"2C" -> Option A

4. Quick Check:

   addr 2 accesses ROM(2) = x"2C" [OK]

Hint: Convert binary address to integer to index ROM [OK]

Common Mistakes:

• Confusing binary "10" as decimal 10
• Using unsigned conversion incorrectly
• Accessing wrong ROM index

4. Identify the error in this VHDL ROM constant array declaration:

constant ROM : array (0 to 3) of std_logic_vector(7 downto 0) := (x"01", x"02", x"03");

medium

A. Hex values must be in single quotes, not double quotes

B. ROM array size does not match the number of elements assigned

C. std_logic_vector cannot be used in constant arrays

D. ROM must be declared as a variable, not constant

Solution

1. Step 1: Check array range and element count

   Array declared from 0 to 3 means 4 elements expected.

2. Step 2: Count assigned elements

   Only 3 elements are assigned, causing a size mismatch error.

3. Final Answer:

   ROM array size does not match the number of elements assigned -> Option B

4. Quick Check:

   Array size must equal element count [OK]

Hint: Match array range with number of elements exactly [OK]

Common Mistakes:

• Assigning fewer elements than declared range
• Misusing quotes for hex literals
• Thinking constants can be variables

5. You want to create a 16-word ROM with 4-bit addresses and 8-bit data using a constant array in VHDL. Which of the following code snippets correctly implements this ROM and reads data based on the address input addr?

hard

A. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (others => (others => '0'));

process(addr) begin
data_out <= ROM(addr);
end process;

B. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0);

process(addr) begin
data_out <= ROM(addr);
end process;

C. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F");

process(addr) begin
data_out <= ROM(to_integer(unsigned(addr)));
end process;

D. constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03");

process(addr) begin
data_out <= ROM(to_integer(unsigned(addr)));
end process;

Solution

1. Step 1: Check ROM declaration size and initialization

   ROM must have 16 elements (0 to 15) each 8-bit wide, fully initialized.

2. Step 2: Verify address conversion and data read

   Address is 4-bit std_logic_vector, converted to integer with to_integer(unsigned(addr)) to index ROM correctly.

3. Step 3: Validate code correctness

   constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; correctly initializes all 16 elements and reads data using proper address conversion.

4. Final Answer:

   constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; -> Option C

5. Quick Check:

   Full initialization + correct address indexing = constant ROM : array (0 to 15) of std_logic_vector(7 downto 0) := (x"00", x"01", x"02", x"03", x"04", x"05", x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E", x"0F"); process(addr) begin data_out <= ROM(to_integer(unsigned(addr))); end process; [OK]

Hint: Initialize all ROM elements and convert address to integer [OK]

Common Mistakes:

• Not initializing all ROM elements
• Using addr directly without conversion
• Declaring ROM without initialization